Design of a 3.3 V Single Power-Supply 64 Mbit Flash Memory with Dynamic Bit-Line Latch (DBL) Programming Scheme

Hiroshi SUGAWARA; Toshio TAKESHIMA; Hiroshi TAKADA; Yoshiaki S. HISAMUNE; Kohji KANAMORI; Takeshi OKAZAWA; Tatsunori MUROTANI; Isao SASAKI

Design of a 3.3 V Single Power-Supply 64 Mbit Flash Memory with Dynamic Bit-Line Latch (DBL) Programming Scheme

Hiroshi SUGAWARA, Toshio TAKESHIMA, Hiroshi TAKADA, Yoshiaki S. HISAMUNE, Kohji KANAMORI, Takeshi OKAZAWA, Tatsunori MUROTANI, Isao SASAKI

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A 3.3 V single power-supply 64 Mb flash memory with a DBL programming scheme has been developed and fabricated with 0.4 µm CMOS technology. 50 ns access time and 256 b erase/programming unit-capacity have been achieved by using hierarchical word- and bit-line structures and DBL programming scheme. Furthermore in order to lower operating voltage the HiCR cell is used. The chip size is 19.3 mm13.3 mm.

Publication: IEICE TRANSACTIONS on Electronics Vol.E78-C No.7 pp.825-831

Publication Date: 1995/07/25

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Type of Manuscript: Special Section PAPER (Special Issue on LSI Memory Device, Circuit, Architecture and Application Technologies for Multimedia Age)

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Hiroshi SUGAWARA, Toshio TAKESHIMA, Hiroshi TAKADA, Yoshiaki S. HISAMUNE, Kohji KANAMORI, Takeshi OKAZAWA, Tatsunori MUROTANI, Isao SASAKI, "Design of a 3.3 V Single Power-Supply 64 Mbit Flash Memory with Dynamic Bit-Line Latch (DBL) Programming Scheme" in IEICE TRANSACTIONS on Electronics, vol. E78-C, no. 7, pp. 825-831, July 1995, doi: .
Abstract: A 3.3 V single power-supply 64 Mb flash memory with a DBL programming scheme has been developed and fabricated with 0.4 µm CMOS technology. 50 ns access time and 256 b erase/programming unit-capacity have been achieved by using hierarchical word- and bit-line structures and DBL programming scheme. Furthermore in order to lower operating voltage the HiCR cell is used. The chip size is 19.3 mm13.3 mm.
URL: https://globals.ieice.org/en_transactions/electronics/10.1587/e78-c_7_825/_p

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@ARTICLE{e78-c_7_825,
author={Hiroshi SUGAWARA, Toshio TAKESHIMA, Hiroshi TAKADA, Yoshiaki S. HISAMUNE, Kohji KANAMORI, Takeshi OKAZAWA, Tatsunori MUROTANI, Isao SASAKI, },
journal={IEICE TRANSACTIONS on Electronics},
title={Design of a 3.3 V Single Power-Supply 64 Mbit Flash Memory with Dynamic Bit-Line Latch (DBL) Programming Scheme},
year={1995},
volume={E78-C},
number={7},
pages={825-831},
abstract={A 3.3 V single power-supply 64 Mb flash memory with a DBL programming scheme has been developed and fabricated with 0.4 µm CMOS technology. 50 ns access time and 256 b erase/programming unit-capacity have been achieved by using hierarchical word- and bit-line structures and DBL programming scheme. Furthermore in order to lower operating voltage the HiCR cell is used. The chip size is 19.3 mm13.3 mm.},
keywords={},
doi={},
ISSN={},
month={July},}

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TY - JOUR
TI - Design of a 3.3 V Single Power-Supply 64 Mbit Flash Memory with Dynamic Bit-Line Latch (DBL) Programming Scheme
T2 - IEICE TRANSACTIONS on Electronics
SP - 825
EP - 831
AU - Hiroshi SUGAWARA
AU - Toshio TAKESHIMA
AU - Hiroshi TAKADA
AU - Yoshiaki S. HISAMUNE
AU - Kohji KANAMORI
AU - Takeshi OKAZAWA
AU - Tatsunori MUROTANI
AU - Isao SASAKI
PY - 1995
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E78-C
IS - 7
JA - IEICE TRANSACTIONS on Electronics
Y1 - July 1995
AB - A 3.3 V single power-supply 64 Mb flash memory with a DBL programming scheme has been developed and fabricated with 0.4 µm CMOS technology. 50 ns access time and 256 b erase/programming unit-capacity have been achieved by using hierarchical word- and bit-line structures and DBL programming scheme. Furthermore in order to lower operating voltage the HiCR cell is used. The chip size is 19.3 mm13.3 mm.
ER -