A Noise-Canceling Charge Pump for Area Efficient PLL Design

Go URAKAWA; Hiroyuki KOBAYASHI; Jun DEGUCHI; Ryuichi FUJIMOTO

doi:10.1587/transele.2020CTP0004

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A Noise-Canceling Charge Pump for Area Efficient PLL Design

Go URAKAWA, Hiroyuki KOBAYASHI, Jun DEGUCHI, Ryuichi FUJIMOTO

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Summary :

In general, since the in-band noise of phase-locked loops (PLLs) is mainly caused by charge pumps (CPs), large-size transistors that occupy a large area are used to improve in-band noise of CPs. With the high demand for low phase noise in recent high-performance communication systems, the issue of the trade-off between occupied area and noise in conventional CPs has become significant. A noise-canceling CP circuit is presented in this paper to mitigate the trade-off between occupied area and noise. The proposed CP can achieve lower noise performance than conventional CPs by performing additional noise cancelation. According to the simulation results, the proposed CP can reduce the current noise to 57% with the same occupied area, or can reduce the occupied area to 22% compared with that of the conventional CPs at the same noise performance. We fabricated a prototype of the proposed CP embedded in a 28-GHz LC-PLL using a 16-nm FinFET process, and 1.2-dB improvement in single sideband integrated phase noise is achieved.

Publication: IEICE TRANSACTIONS on Electronics Vol.E104-C No.10 pp.625-634

Publication Date: 2021/10/01

Publicized: 2021/04/20

Online ISSN: 1745-1353

DOI: 10.1587/transele.2020CTP0004

Type of Manuscript: Special Section PAPER (Special Section on Analog Circuits and Their Application Technologies)

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Authors

Go URAKAWA
  Kioxia Corporation
Hiroyuki KOBAYASHI
  Kioxia Corporation
Jun DEGUCHI
  Kioxia Corporation
Ryuichi FUJIMOTO
  Kioxia Corporation

Keyword

PLL, frequency synthesizer, phase-locked loop, charge pump, noise-cancel, phase noise, jitter, in-band noise, occupied area

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Go URAKAWA, Hiroyuki KOBAYASHI, Jun DEGUCHI, Ryuichi FUJIMOTO, "A Noise-Canceling Charge Pump for Area Efficient PLL Design" in IEICE TRANSACTIONS on Electronics, vol. E104-C, no. 10, pp. 625-634, October 2021, doi: 10.1587/transele.2020CTP0004.
Abstract: In general, since the in-band noise of phase-locked loops (PLLs) is mainly caused by charge pumps (CPs), large-size transistors that occupy a large area are used to improve in-band noise of CPs. With the high demand for low phase noise in recent high-performance communication systems, the issue of the trade-off between occupied area and noise in conventional CPs has become significant. A noise-canceling CP circuit is presented in this paper to mitigate the trade-off between occupied area and noise. The proposed CP can achieve lower noise performance than conventional CPs by performing additional noise cancelation. According to the simulation results, the proposed CP can reduce the current noise to 57% with the same occupied area, or can reduce the occupied area to 22% compared with that of the conventional CPs at the same noise performance. We fabricated a prototype of the proposed CP embedded in a 28-GHz LC-PLL using a 16-nm FinFET process, and 1.2-dB improvement in single sideband integrated phase noise is achieved.
URL: https://globals.ieice.org/en_transactions/electronics/10.1587/transele.2020CTP0004/_p

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@ARTICLE{e104-c_10_625,
author={Go URAKAWA, Hiroyuki KOBAYASHI, Jun DEGUCHI, Ryuichi FUJIMOTO, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Noise-Canceling Charge Pump for Area Efficient PLL Design},
year={2021},
volume={E104-C},
number={10},
pages={625-634},
abstract={In general, since the in-band noise of phase-locked loops (PLLs) is mainly caused by charge pumps (CPs), large-size transistors that occupy a large area are used to improve in-band noise of CPs. With the high demand for low phase noise in recent high-performance communication systems, the issue of the trade-off between occupied area and noise in conventional CPs has become significant. A noise-canceling CP circuit is presented in this paper to mitigate the trade-off between occupied area and noise. The proposed CP can achieve lower noise performance than conventional CPs by performing additional noise cancelation. According to the simulation results, the proposed CP can reduce the current noise to 57% with the same occupied area, or can reduce the occupied area to 22% compared with that of the conventional CPs at the same noise performance. We fabricated a prototype of the proposed CP embedded in a 28-GHz LC-PLL using a 16-nm FinFET process, and 1.2-dB improvement in single sideband integrated phase noise is achieved.},
keywords={},
doi={10.1587/transele.2020CTP0004},
ISSN={1745-1353},
month={October},}

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TY - JOUR
TI - A Noise-Canceling Charge Pump for Area Efficient PLL Design
T2 - IEICE TRANSACTIONS on Electronics
SP - 625
EP - 634
AU - Go URAKAWA
AU - Hiroyuki KOBAYASHI
AU - Jun DEGUCHI
AU - Ryuichi FUJIMOTO
PY - 2021
DO - 10.1587/transele.2020CTP0004
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E104-C
IS - 10
JA - IEICE TRANSACTIONS on Electronics
Y1 - October 2021
AB - In general, since the in-band noise of phase-locked loops (PLLs) is mainly caused by charge pumps (CPs), large-size transistors that occupy a large area are used to improve in-band noise of CPs. With the high demand for low phase noise in recent high-performance communication systems, the issue of the trade-off between occupied area and noise in conventional CPs has become significant. A noise-canceling CP circuit is presented in this paper to mitigate the trade-off between occupied area and noise. The proposed CP can achieve lower noise performance than conventional CPs by performing additional noise cancelation. According to the simulation results, the proposed CP can reduce the current noise to 57% with the same occupied area, or can reduce the occupied area to 22% compared with that of the conventional CPs at the same noise performance. We fabricated a prototype of the proposed CP embedded in a 28-GHz LC-PLL using a 16-nm FinFET process, and 1.2-dB improvement in single sideband integrated phase noise is achieved.
ER -