Doherty Amplifier Design Based on Asymmetric Configuration Scheme

Ryo ISHIKAWA; Yoichiro TAKAYAMA; Kazuhiko HONJO

doi:10.1587/transele.2021MMI0002

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Doherty Amplifier Design Based on Asymmetric Configuration Scheme

Ryo ISHIKAWA, Yoichiro TAKAYAMA, Kazuhiko HONJO

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Summary :

A practical Doherty amplifier design method has been developed based on an asymmetric configuration scheme. By embedding a load modulation function into matching circuits of a carrier amplifier (CA) and a peaking amplifier (PA) in the Doherty amplifier, an issue of the Doherty amplifier design is boiled down to the CA and PA matching circuit design. The method can be applied to transistors with unknown parasitic elements if optimum termination impedance conditions for the transistor are obtained from a source-/load-pull technique in simulation or measurement. The design method was applied to GaN HEMT Doherty amplifier MMICs. The fabricated 4.5-GHz-band GaN HEMT Doherty amplifier MMIC exhibited a maximum drain efficiency of 66% and a maximum power-added efficiency (PAE) of 62% at 4.1GHz, with a saturation output power of 36dBm. In addition, PAE of 50% was achieved at 4.1GHz on a 7.2-dB output back-off (OBO) condition. The fabricated 8.5-GHz-band GaN HEMT Doherty amplifier MMIC exhibited a maximum drain efficiency of 53% and a maximum PAE of 44% at 8.6GHz, with a saturation output power of 36dBm. In addition, PAE of 35% was achieved at 8.6GHz on a 6.7-dB (OBO). And, the fabricated 12-GHz-band GaN HEMT Doherty amplifier MMIC exhibited a maximum drain efficiency of 57% and a maximum PAE of 52% at 12.4GHz, with a saturation output power of 34dBm. In addition, PAE of 32% was achieved at 12.4GHz on a 9.5-dB (OBO) condition.

Publication: IEICE TRANSACTIONS on Electronics Vol.E104-C No.10 pp.496-505

Publication Date: 2021/10/01

Publicized: 2021/04/16

Online ISSN: 1745-1353

DOI: 10.1587/transele.2021MMI0002

Type of Manuscript: Special Section INVITED PAPER (Special Section on Microwave and Millimeter-Wave Technologies)

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Authors

Ryo ISHIKAWA
  the University of Electro-Communications
Yoichiro TAKAYAMA
  the University of Electro-Communications
Kazuhiko HONJO
  the University of Electro-Communications

Keyword

wireless communication, doherty power amplifier, asymmetric configuration, GaN HEMT MMIC

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Ryo ISHIKAWA, Yoichiro TAKAYAMA, Kazuhiko HONJO, "Doherty Amplifier Design Based on Asymmetric Configuration Scheme" in IEICE TRANSACTIONS on Electronics, vol. E104-C, no. 10, pp. 496-505, October 2021, doi: 10.1587/transele.2021MMI0002.
Abstract: A practical Doherty amplifier design method has been developed based on an asymmetric configuration scheme. By embedding a load modulation function into matching circuits of a carrier amplifier (CA) and a peaking amplifier (PA) in the Doherty amplifier, an issue of the Doherty amplifier design is boiled down to the CA and PA matching circuit design. The method can be applied to transistors with unknown parasitic elements if optimum termination impedance conditions for the transistor are obtained from a source-/load-pull technique in simulation or measurement. The design method was applied to GaN HEMT Doherty amplifier MMICs. The fabricated 4.5-GHz-band GaN HEMT Doherty amplifier MMIC exhibited a maximum drain efficiency of 66% and a maximum power-added efficiency (PAE) of 62% at 4.1GHz, with a saturation output power of 36dBm. In addition, PAE of 50% was achieved at 4.1GHz on a 7.2-dB output back-off (OBO) condition. The fabricated 8.5-GHz-band GaN HEMT Doherty amplifier MMIC exhibited a maximum drain efficiency of 53% and a maximum PAE of 44% at 8.6GHz, with a saturation output power of 36dBm. In addition, PAE of 35% was achieved at 8.6GHz on a 6.7-dB (OBO). And, the fabricated 12-GHz-band GaN HEMT Doherty amplifier MMIC exhibited a maximum drain efficiency of 57% and a maximum PAE of 52% at 12.4GHz, with a saturation output power of 34dBm. In addition, PAE of 32% was achieved at 12.4GHz on a 9.5-dB (OBO) condition.
URL: https://globals.ieice.org/en_transactions/electronics/10.1587/transele.2021MMI0002/_p

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@ARTICLE{e104-c_10_496,
author={Ryo ISHIKAWA, Yoichiro TAKAYAMA, Kazuhiko HONJO, },
journal={IEICE TRANSACTIONS on Electronics},
title={Doherty Amplifier Design Based on Asymmetric Configuration Scheme},
year={2021},
volume={E104-C},
number={10},
pages={496-505},
abstract={A practical Doherty amplifier design method has been developed based on an asymmetric configuration scheme. By embedding a load modulation function into matching circuits of a carrier amplifier (CA) and a peaking amplifier (PA) in the Doherty amplifier, an issue of the Doherty amplifier design is boiled down to the CA and PA matching circuit design. The method can be applied to transistors with unknown parasitic elements if optimum termination impedance conditions for the transistor are obtained from a source-/load-pull technique in simulation or measurement. The design method was applied to GaN HEMT Doherty amplifier MMICs. The fabricated 4.5-GHz-band GaN HEMT Doherty amplifier MMIC exhibited a maximum drain efficiency of 66% and a maximum power-added efficiency (PAE) of 62% at 4.1GHz, with a saturation output power of 36dBm. In addition, PAE of 50% was achieved at 4.1GHz on a 7.2-dB output back-off (OBO) condition. The fabricated 8.5-GHz-band GaN HEMT Doherty amplifier MMIC exhibited a maximum drain efficiency of 53% and a maximum PAE of 44% at 8.6GHz, with a saturation output power of 36dBm. In addition, PAE of 35% was achieved at 8.6GHz on a 6.7-dB (OBO). And, the fabricated 12-GHz-band GaN HEMT Doherty amplifier MMIC exhibited a maximum drain efficiency of 57% and a maximum PAE of 52% at 12.4GHz, with a saturation output power of 34dBm. In addition, PAE of 32% was achieved at 12.4GHz on a 9.5-dB (OBO) condition.},
keywords={},
doi={10.1587/transele.2021MMI0002},
ISSN={1745-1353},
month={October},}

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TY - JOUR
TI - Doherty Amplifier Design Based on Asymmetric Configuration Scheme
T2 - IEICE TRANSACTIONS on Electronics
SP - 496
EP - 505
AU - Ryo ISHIKAWA
AU - Yoichiro TAKAYAMA
AU - Kazuhiko HONJO
PY - 2021
DO - 10.1587/transele.2021MMI0002
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E104-C
IS - 10
JA - IEICE TRANSACTIONS on Electronics
Y1 - October 2021
AB - A practical Doherty amplifier design method has been developed based on an asymmetric configuration scheme. By embedding a load modulation function into matching circuits of a carrier amplifier (CA) and a peaking amplifier (PA) in the Doherty amplifier, an issue of the Doherty amplifier design is boiled down to the CA and PA matching circuit design. The method can be applied to transistors with unknown parasitic elements if optimum termination impedance conditions for the transistor are obtained from a source-/load-pull technique in simulation or measurement. The design method was applied to GaN HEMT Doherty amplifier MMICs. The fabricated 4.5-GHz-band GaN HEMT Doherty amplifier MMIC exhibited a maximum drain efficiency of 66% and a maximum power-added efficiency (PAE) of 62% at 4.1GHz, with a saturation output power of 36dBm. In addition, PAE of 50% was achieved at 4.1GHz on a 7.2-dB output back-off (OBO) condition. The fabricated 8.5-GHz-band GaN HEMT Doherty amplifier MMIC exhibited a maximum drain efficiency of 53% and a maximum PAE of 44% at 8.6GHz, with a saturation output power of 36dBm. In addition, PAE of 35% was achieved at 8.6GHz on a 6.7-dB (OBO). And, the fabricated 12-GHz-band GaN HEMT Doherty amplifier MMIC exhibited a maximum drain efficiency of 57% and a maximum PAE of 52% at 12.4GHz, with a saturation output power of 34dBm. In addition, PAE of 32% was achieved at 12.4GHz on a 9.5-dB (OBO) condition.
ER -