A MPEG-4 Video Codec Chip with Low Power Scheme for Mobile Application

Seongmo PARK; Miyoung LEE; KyoungSeon SHIN; Hanjin CHO; Jongdae KIM; Dukdong LEE

A MPEG-4 Video Codec Chip with Low Power Scheme for Mobile Application

Seongmo PARK, Miyoung LEE, KyoungSeon SHIN, Hanjin CHO, Jongdae KIM, Dukdong LEE

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In this paper, we present a design of MPEG-4 video codec chip to reduce the power consumption using frame level clock gating, macro block level and motion estimation skip scheme. It performs 30 frames/s of codec (encoding and decoding) mode with quarter-common intermediate format (QCIF) at 27 MHz. Power consumption is 290 mW at 27 MHz operation, which is achieving 35% power saving compared to a conventional CMOS. Motion Estimation skip method is employed to reduce 32% computation load. This chip performs MPEG-4 Simple Profile Level 2 (Simple@L2) and H. 263 base mode. Its contains 388,885 gates, 662 k bits memory, and the chip size was 9.7 mm9.7 mm which was fabricated using 0.35 micron 3-layers metal CMOS technology.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E86-A No.6 pp.1353-1363

Publication Date: 2003/06/01

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Type of Manuscript: Special Section PAPER (Special Section on Papers Selected from 2002 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2002))

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Seongmo PARK, Miyoung LEE, KyoungSeon SHIN, Hanjin CHO, Jongdae KIM, Dukdong LEE, "A MPEG-4 Video Codec Chip with Low Power Scheme for Mobile Application" in IEICE TRANSACTIONS on Fundamentals, vol. E86-A, no. 6, pp. 1353-1363, June 2003, doi: .
Abstract: In this paper, we present a design of MPEG-4 video codec chip to reduce the power consumption using frame level clock gating, macro block level and motion estimation skip scheme. It performs 30 frames/s of codec (encoding and decoding) mode with quarter-common intermediate format (QCIF) at 27 MHz. Power consumption is 290 mW at 27 MHz operation, which is achieving 35% power saving compared to a conventional CMOS. Motion Estimation skip method is employed to reduce 32% computation load. This chip performs MPEG-4 Simple Profile Level 2 (Simple@L2) and H. 263 base mode. Its contains 388,885 gates, 662 k bits memory, and the chip size was 9.7 mm9.7 mm which was fabricated using 0.35 micron 3-layers metal CMOS technology.
URL: https://globals.ieice.org/en_transactions/fundamentals/10.1587/e86-a_6_1353/_p

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@ARTICLE{e86-a_6_1353,
author={Seongmo PARK, Miyoung LEE, KyoungSeon SHIN, Hanjin CHO, Jongdae KIM, Dukdong LEE, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A MPEG-4 Video Codec Chip with Low Power Scheme for Mobile Application},
year={2003},
volume={E86-A},
number={6},
pages={1353-1363},
abstract={In this paper, we present a design of MPEG-4 video codec chip to reduce the power consumption using frame level clock gating, macro block level and motion estimation skip scheme. It performs 30 frames/s of codec (encoding and decoding) mode with quarter-common intermediate format (QCIF) at 27 MHz. Power consumption is 290 mW at 27 MHz operation, which is achieving 35% power saving compared to a conventional CMOS. Motion Estimation skip method is employed to reduce 32% computation load. This chip performs MPEG-4 Simple Profile Level 2 (Simple@L2) and H. 263 base mode. Its contains 388,885 gates, 662 k bits memory, and the chip size was 9.7 mm9.7 mm which was fabricated using 0.35 micron 3-layers metal CMOS technology.},
keywords={},
doi={},
ISSN={},
month={June},}

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TY - JOUR
TI - A MPEG-4 Video Codec Chip with Low Power Scheme for Mobile Application
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1353
EP - 1363
AU - Seongmo PARK
AU - Miyoung LEE
AU - KyoungSeon SHIN
AU - Hanjin CHO
AU - Jongdae KIM
AU - Dukdong LEE
PY - 2003
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E86-A
IS - 6
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - June 2003
AB - In this paper, we present a design of MPEG-4 video codec chip to reduce the power consumption using frame level clock gating, macro block level and motion estimation skip scheme. It performs 30 frames/s of codec (encoding and decoding) mode with quarter-common intermediate format (QCIF) at 27 MHz. Power consumption is 290 mW at 27 MHz operation, which is achieving 35% power saving compared to a conventional CMOS. Motion Estimation skip method is employed to reduce 32% computation load. This chip performs MPEG-4 Simple Profile Level 2 (Simple@L2) and H. 263 base mode. Its contains 388,885 gates, 662 k bits memory, and the chip size was 9.7 mm9.7 mm which was fabricated using 0.35 micron 3-layers metal CMOS technology.
ER -