1-2hit |
Akio NAKATA Teruo HIGASHINO Kenichi TANIGUCHI
Verification of timed bisimulation equivalence is generally difficult because of the state explosion caused by concrete time values. In this paper, we propose a verification method to verify timed bisimulation equivalence of two timed processes using a symbolic technique similar to [1]. We first propose a new model of timed processes, Alternating Timed Symbolic Labelled Transition System (A-TSLTS). In an A-TSLTS, each state has some parameter variables, whose values determine its behaviour. Each transition in an A-TSLTS has a quard predicate. The transition is executable if and only if its guard predicate is true underspecified parameter values. In the proposed method, we can obtain the weakest condition for a state-pair in a finite A-TSLTS, which the parameter values in the weakest condition must satisfy to make the state-pair be timed bisimulation equivalent.
Tadaaki TANIMOTO Akio NAKATA Hideaki HASHIMOTO Teruo HIGASHINO
In this paper, we propose a parametric model checking algorithm for a subclass of Timed Automata called Parametric Time-Interval Automata (PTIA). In a PTIA, we can specify upper- and lower-bounds of the execution time (time-interval) of each transition using parameter variables. The proposed algorithm takes two inputs, a model described in a PTIA and a property described in a PTIA accepting all invalid infinite/finite runs (called a never claim), or valid finite runs of the model. In the proposed algorithm, firstly we determinize and complement the given property PTIA if it accepts valid finite runs. Secondly, we accelerate the given model, that is, we regard all the actions that are not appeared in the given property PTIA as invisible actions and eliminate them from the model while preserving the set of visible traces and their timings. Thirdly, we construct a parallel composition of the model and the property PTIAs which is accepting all invalid runs that are accepted by the model. Finally, we perform the extension of Double Depth First Search (DDFS), which is used in the automata-theoretic approach to Linear-time Temporal Logic (LTL) model checking, to derive the weakest parameter condition in order that the given model never executes the invalid runs specified by the given property.