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[Author] Akio TAKAGI(1hit)
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A 120-Gbit/s 1.27-W 520-mVpp 2:1 Multiplexer IC Using Self-Aligned InP/InGaAs/InP DHBTs with Emitter Mesa Passivation
Yutaka ARAYASHIKI Yukio OHKUBO Taisuke MATSUMOTO Yoshiaki AMANO Akio TAKAGI Yutaka MATSUOKA
- PAPER-III-V High-Speed Devices and Circuits
- Vol:
- E93-C No:8
- Page(s):
- 1273-1278
We fabricated a 2:1 multiplexer IC (MUX) with a retiming function by using 1-µm self-aligned InP/InGaAs/InP double-heterojunction bipolar transistors (DHBTs) with emitter mesa passivation ledges. The MUX operated at 120 Gbit/s with a power dissipation of 1.27 W and output amplitude of 520 mV when measured on the wafer. When assembled in a module using V-connectors, the MUX operated at 113 Gbit/s with a 514-mV output amplitude and a power dissipation of 1.4 W.
