In this paper, we propose an algorithm to convert a given structured LOTOS specification into an equivalent flattened model called synchronous EFSMs. The synchronous EFSMs model is an execution model for communication protocols and distributed systems where each system consists of concurrent EFSMs and a finite set of multi-rendezvous indications among their subsets. The EFSMs can be derived from a specification in a sub-class of LOTOS and its implementation becomes simpler than the straightforward implementation of the original LOTOS specification because the synchronization among the processes in the model does not have any child-parent relationships, which can make the synchronization mechanism much more complex. Some experimental results are reported to show the advantage of synchronous EFSMs in terms of execution efficiency.

In this paper, an architecture of multi-threaded processor for embedded systems is proposed and evaluated comparing with other processors for embedded systems. The experimental results show the trade-off of hardware costs and execution times among processors. Taking proposed multi-threaded processor into account as an embedded processor, design space of embedded systems are enlarged and more suitable architecture can be selected under some design constraints.

In this paper, we propose a technique to synthesize a hardware circuit from a protocol specification consisting of several concurrent EFSMs with multi-rendezvous specified among their subsets. In our class, each multi-rendezvous can be specified among more than two EFSMs, and several multi-rendezvous can be specified for different combinations of EFSMs. In the proposed technique, using the information such as current states of EFSMs, input values at external gates and guard expressions, we compose a circuit to evaluate whether each multi-rendezvous can be executed. If several exclusive multi-rendezvous get executable simultaneously for some combinations of EFSMs, we select one of them according to the priority order given in advance. We compose such a circuit as a combinational logic circuit so that it works fast. By applying our technique to Abracadabra protocol specified in LOTOS, it is confirmed that the derived circuit handles multi-rendezvous efficiently.