This paper proposes a high-efficiency on-chip DC-DC down-conversion technique using selectable supply-voltage charge-recycling. This technique converts an external high supply-voltage (2VDD) to an on-chip low supply-voltage (VDD) by using charge-recycling. It partitions the original logic using VDD into high logic (H-logic) and low logic (L-logic), consuming nearly the same amount of power. The H-logic uses a higher supply-voltage (2VDD and VDD). The L-logic uses a lower supply-voltage (VDD and ground). The charge used in the H-logic is recycled in the L-logic. In order to reduce a charge mismatch between the H-logic and the L-logic, this scheme dynamically changes the ratio between the H-logic and the L-logic by selecting the supply-voltages used by the divided logic blocks. To verify the DC-DC down-conversion using the proposed charge-recycling scheme, a test chip was fabricated using a 0.35 µm CMOS technology. Its power efficiency was measured at 93%.