This letter proposes a wideband compact DC block design technique. This DC block has a wide pass-band and wide stop-band and transforms termination impedances. It comprises a pair of coupled lines on a defected ground structure (DGS) with capacitor loading. A periodic DGS pattern increases coupling, and, consequently, a wideband DC block design is allowed with a microstrip process on a high dielectric low height substrate. A DC block with equal termination impedances of 50,$Omega$ and another that transforms 50 into 30,$Omega$ are fabricated. The measured fractional bandwidths are 48% and 47%. The size of the DC block is 16.8$ imes$ 15,mm$^2(0.057lambda_0 imes 0.051lambda_0)$.

This paper proposes a high clutter-rejection technique for wall-penetrating frequency-modulated continuous-wave (FMCW) radar. FMCW radars are widely used, as they moderate the receiver saturation problem in wall-penetrating applications by attenuating short-range clutter such as wall-clutter. However, conventional FMCW radars require a very high-order high-pass filter (HPF) to attenuate short-range clutter. A delay-line (DL) is exploited to overcome this problem. Time-delay shifts beat frequencies formed by reflection waves. This means that a proper time-delay increases the ratio of target-beat frequency to clutter-beat frequency. Consequently, low-order HPF fully attenuates short-range clutter. A third-order HPF rejects more than 20 dB and 30 dB for clutter located at 6 m and 3 m, respectively, with a target located at 9 m detection with a 10,000 GHz/s chirp rate and a 28 ns delay-line.

This paper presents a design optimization method for a Gm-C active filter via geometric programming (GP). We first describe a GP-compatible model of a cascaded Gm-C filter that forms a biquadratic output transfer function. The bias, gain, bandwidth, and signal-to-noise ratio (SNR) of the Gm-C filter are described in a GP-compatible way. To further enhance the accuracy of the model, two modeling techniques are introduced. The first, a two-step selection method, chooses whether a saturation or subthreshold model should be used for each transistor in the filter to enhance the modeling accuracy. The second, a bisection method, is applied to include non-posynomial inequalities in the filter modeling. The presented filter model is optimized via a GP solver along with proposed modeling techniques. The numerical experiments over wide ranges of design specifications show good agreement between model and simulation results, with the average error for gain, bandwidth, and SNR being less than 9.9%, 4.4%, and 14.6%, respectively.

A wideband noise-cancelling receiver front-end is proposed in this brief. As a basic architecture, a low-noise transconductance amplifier, a passive mixer, and a transimpedance amplifier are employed to compose the wideband receiver. To achieve wideband input matching for the transconductor, a global feedback method is adopted. Since the wideband receiver has to minimize linearity degradation if a large blocker signal exists out-of-band, a linearization technique is applied for the transconductor circuit. The linearization cancels third-order intermodulation distortion components and increases linearity; however, the additional circuits used in linearization generate excessive noise. A noise-cancelling architecture that employs an auxiliary path cancels noise signals generated in the main path. The designed receiver front-end is fabricated using a 65-nm CMOS process. The receiver operates in the frequency range of 25 MHz-2 GHz with a gain of 49.7 dB. The in-band input-referred third-order intercept point is improved by 12.3 dB when the linearization is activated, demonstrating the effectiveness of the linearization technique.