In an effort to reduce switch cost, we present the optimum numbers of tunable wavelength converters (TWCs) and internal wavelengths required for contention resolution of asynchronous and variable length packets, in the optical packet switch (OPS) with the shared fiber delay line (FDL) buffer. To optimize TWCs and internal wavelengths related to OPS design cost, we proposed a scheduling algorithm for the limited TWCs and internal wavelengths. For three TWC alternatives (not shared, partially shared, and fully shared cases), the optimum numbers of TWCs and internal wavelengths to guarantee minimum packet loss are evaluated to prevent resource waste. Under a given load, TWCs and internal wavelengths could be significantly reduced, guaranteeing the same packet loss as the performance of an OPS with full TWCs and internal wavelengths.

We propose an optical packet switch (OPS) using a hybrid buffer structure for the contention resolution of asynchronous variable length packets. The hybrid buffer consists of a fiber delay line (FDL) buffer as the prime buffer and a shared electronic buffer as the supplementary buffer. For the performance evaluation, a modified void filling scheduling algorithm that can be applied to the OPS was proposed. Simulation results show that the use of the electronic buffer together with the FDL buffer significantly reduce the number of FDLs required for contention resolution and considerably lower packet loss.

We present and demonstrate a novel method of generating a π phase-alternated return-to-zero (RZ) signal together with pulse-amplitude equalization in a rational harmonic mode-locked fiber ring laser, by using a dual-drive Mach-Zehnder modulator. By adjusting the voltages applied to both arms of the modulator, amplitude-equalization and π phase shift can be achieved successfully at a 9.95 GHz repetition rate. The generated alternate-phase RZ signals show enhanced transmission performance in the single-mode fiber (SMF) links without dispersion compensation.

Existing forwarding strategies for delay tolerant networks aim at network throughput maximization. They provide forwarding opportunities to more reachable destinations. This results in the long end-to-end delay and low throughput of less reachable destinations. In this paper, we propose two forwarding strategies to improve the throughput of less reachable nodes with little throughput degradation of more reachable nodes. Evaluation results show that the proposed forwarding strategies can control the levels of fairness among the destinations while maintaining high throughput, compared with the legacy forwarding strategies.

The authors propose and experimentally demonstrate an all-optical exclusive OR (XOR) logic gate based on self-phase modulation (SPM) of a semiconductor optical amplifier (SOA). The scheme is insensitive to the polarization of the input signal and requires no additional synchronized clock. The output of the XOR gate showed the contrast ratio of more than 17 dB for the input signal at 2.5 GHz.

We propose a simple technique for reducing the jitter of the output clock generated in the clock recovery circuit (CRC) for burst-mode data transmission. By using this technique, the proposed CRC based on the gated oscillator (GO) can recover the output clock with a low-jitter even when there are consecutive same data streams encountered in the system. The circuit is composed only of digital logic devices and can recover the input data errorless until 1,000 consecutive same data bits are incoming.