Power-aware scheduling of periodic tasks in real-time systems has been extensively studied to save energy while still meeting the performance requirement. Many previous studies use the probability information of tasks' execution cycles to assist the scheduling. However, most of these approaches adopt heuristic algorithms to cope with realistic CPU models with discrete frequencies and cannot achieve the globally optimal solution. Sometimes they even show worse results than non-stochastic DVS schemes. This paper presents an optimal DVS scheme for frame-based real-time systems under realistic power models in which the processor provides only a limited number of speeds and no assumption is made on power/frequency relation. A suboptimal DVS scheme is also presented in this paper to work out a solution near enough to the optimal one with only polynomial time expense. Experiment results show that the proposed algorithm can save at most 40% more energy compared with previous ones.

Multi-pattern matching is a key technique for implementing network security applications such as Network Intrusion Detection/Protection Systems (NIDS/NIPSes) where every packet is inspected against tens of thousands of predefined attack signatures written in regular expressions (regexes). To this end, Deterministic Finite Automaton (DFA) is widely used for multi-regex matching, but existing DFA-based researches have claimed high throughput at an expense of extremely high memory cost, so fail to be employed in devices such as high-speed routers and embedded systems where the available memory is quite limited. In this paper, we propose a parallel architecture of DFA called Parallel DFA (PDFA) taking advantage of the large amount of concurrent flows to increase the throughput with nearly no extra memory cost. The basic idea is to selectively store the underlying DFA in memory modules that can be accessed in parallel. To explore its potential parallelism we intensively study DFA-split schemes from both state and transition points in this paper. The performance of our approach in both the average cases and the worst cases is analyzed, optimized and evaluated by numerical results. The evaluation shows that we obtain an average speedup of 100 times compared with traditional DFA-based matching approach.

We present distributed load balancing mechanisms implemented on multiprocessor systems for real time video encoding, which dynamically equalize load amounts among PE's to cope with extensive computing requirements. The loosely coupled multiprocessor system, e.g. a torus connected one, is treated as the objective system. Two decentralized controlled load balancicg algorithms are proposed, and mathematical analyses are provided to obtain some insights of our decentralized controlled mechanisms. We also prove the proposed algorithms are steady and effective theoretically and experimentally.

This paper introduces the new application specific architecture RHINE (Reconfigurable Hierarchical Image Neo-multiprocessor Engine) that is a multiprocessor system for moving picture CODEC. The array processor is known to be originally suited for data parallel processing such as image signal processing which requires vast amount of computations and has the identical instruction sequences on data. However, the moving picture CODEC algorithm suffers from the large load imbalance in the processings on multi-processors with the separated sub-images. Some load balancing techniques are indispensable in such applications for the highest speed-up. RHINE gives one of the optimal solutions for such a load balancing due to its feature of the self reconfigurable architecture. RHINE consists of Block Processing Units (BPU) hierarchically, in each of which has a common bus architecture of multiprocessors with a block memory. Processors in a BPU move to the other BPU according to the load imbalance between BPUs by switching the bus connection between BPUs. The advantage of RHINE architecture is demonstrated by showing performance simulations for real moving pictures.

In this paper, performance degradation of satellite broadcasting receiving antenna systems due to weather conditions is examined by measuring their G/T continuously. We show that an offset parabolic reflector antenna of smaller aperture tends to be less affected by weather conditions.

Dynamic Voltage Scaling (DVS) is a well-known low-power design technique, which adjusts the clock speed and supply voltage dynamically to reduce the energy consumption of real-time systems. Previous studies considered the probabilistic distribution of tasks' workloads to assist DVS in task scheduling. These studies use probability information for intra-task frequency scheduling but do not sufficiently explore the opportunities for the system workload to save more energy. This paper presents a novel DVS algorithm for periodic real-time tasks based on the analysis of the system workload to reduce its power consumption. This algorithm takes full advantage of the probabilistic distribution characteristics of the system workload under priority-driven scheduling such as Earliest-Deadline-First (EDF). Experimental results show that the proposed algorithm reduces processor idle time and spends more busy time in lower-power speeds. The measurement indicates that compared to the relative DVS algorithms, this algorithm saves energy by at least 30% while delivering statistical performance guarantees.

This paper is in response to the report of Ahn, Mun, Kim, Oh, and Han published in IEICE Trans. INF. & SYST., Vol.E91-D, No.4, 2008, 1215-1217. They tried to extend their previous paper that published on IEICE Trans. INF. & SYST., Vol.E86-D, No.12, 2003, 2790-2793. However, we will point out that their extension is based on the detailed data of knowing the frequency of three types. Their new occurrence information based on intuitionistic fuzzy set for medical diagnosis of headache becomes redundant. We advise researchers to directly use the detailed data to decide the diagnosis of headache.

This letter realizes direction of arrival (DOA) estimation by exploiting the noise subspace based estimator. Since single subspace feature extraction fails to achieve satisfactory results under unknown noise fields, we propose a two-step subspace feature extraction technique that is effective even in these fields. When a new noise subspace is attained, the proposed estimator without prewhitening can form the maximizing orthogonality especially for unknown noise fields. Simulation results confirm the effectiveness of the proposed technique.

Several papers have presented measured function to handle multi-criteria fuzzy decision-making problems based on interval-valued intuitionistic fuzzy sets. However, in some cases, the proposed function cannot give sufficient information about alternatives. Consequently, in this paper, we will overcome previous insufficient problem and provide a novel accuracy function to measure the degree of the interval-valued intuitionistic fuzzy information. And a practical example has been provided to demonstrate our proposed approach. In addition, to make computing and ranking results easier and to increase the recruiting productivity, a computer-based interface system has been developed for decision makers to make decisions more efficiently.

In this paper, under the assumption that all the eigenvalues of a linear nominal discrete time-delay system lie within a specified ring region, a sufficient condition is proposed to preserve the assumed property when the structured parameter perturbations are added into the linear nominal discrete time-delay system. For the case of eigenvalue-clustering in a circular region, and for the case of not including time delays, the presented sufficient condition is mathematically proved to be less conservative than those reported recently in the literature.

Amplitude phase shift keying (APSK) constellation with Gray mapping was proposed recently. Inspired by the simplified soft demapping for regular Gray-QAM, a simplified soft demapping algorithm for Gray-APSK is proposed in this paper. Compared with conventional soft demapping schemes, its complexity is greatly reduced with only a little SNR loss, which is validated by the complexity analysis and FPGA compilation results.