In this paper, the influence of surface waves on the characteristics of on-glass antennas is clarified to enable appropriates design of C-band automotive on-glass antennas. Composite glasses are used in automotive windshields. These automotive composite glasses are composed of three layers. First, the surface wave properties of composite glass are investigated. Next, the effects of surface waves on the reflection coefficient characteristics of on-glass antennas are investigated. Finally, the antenna placement to reduce surface wave effect will be presented. Electromagnetic field analysis of a dipole antenna placed at the center of a 300mm × 300mm square flat composite glass showed that the electric field strength in the glass had ripples with the half wavelength period of the surface waves. Therefore, it was confirmed that standing waves are generated because of these surface waves. In addition, it is confirmed that ripples occur in the reflection coefficient at frequencies. Glass size is divisible by each of those guide wavelengths. Furthermore, it was clarified that the reflection coefficient fluctuates with respect to the distance between the antenna and a metal frame, which is attached to the end face in the direction perpendicular to the thickness of the glass because of the influence of standing waves caused by the surface waves; additionally, the reflection coefficient gets worse when the distance between the antenna and the metal frame is an integral multiple of one half wavelength. A similar tendency was observed in an electric field analysis using a model that was shaped like the actual windshield shape. Because radiation patterns also change as a result of the influence of surface waves and metal frames, the results imply that it is necessary to consider the actual device size and the metal frames when designing automotive on-glass antennas.

Delay Tolerant Networks (DTNs) are vulnerable to message flooding attacks in which a very large number of malicious messages are sent so that network resources are depleted. To address this problem, previous studies mainly focused on constraining the number of messages that nodes can generate per time slot by allowing nodes to monitor the other nodes' communication history. Since the adversaries may hide their attacks by claiming a false history, nodes exchange their communication histories and detect an attacker who has presented an inconsistent communication history. However, this approach increases node energy consumption since the number of communication histories increases every time a node communicates with another node. To deal with this problem, in this paper, we propose an energy-efficient defense against such message flooding attacks. The main idea of the proposed scheme is to time limit the communication history exchange so as to reduce the volume while ensuring the effective detection of inconsistencies. The advantage of this approach is that, by removing communication histories after they have revealed such inconsistencies, the energy consumption is reduced. To estimate such expiration time, analytical expressions based upon a Markov chain based message propagation model, are derived for the probability that a communication history reveals such inconsistency in an arbitrary time. Extensive performance evaluation results obtained by means of computer simulations and several performance criteria verify that the proposed scheme successfully improves the overall energy efficiency. For example, these performance results have shown that, as compared to other previously known defenses against message flooding attacks, the proposed scheme extends by at least 22% the battery lifetime of DTN nodes, while maintaining the same levels of protection.

This letter presents a low-power switched current (SI) memory cell with CMOS-type configuration. By combining nMOS and pMOS in the SI memory cell and using a polarity discrimination circuit, we design a CMOS-type SI memory cell which eliminates the quiescent current in the SI memory cell. The simulation result shows that the CMOS-type SI memory cell consumes less power than the conventional class-AB memory cell.

A flexible and low-cost menagement technology is desired for fabrication line of both ASICs and cutting edge LSIs. To meet such desire, a management technology named "super operator shifts" has been proposed. After taking operator's skill level into consideration, an ASIC line manager can stretch line working time by use of the super operator shifts. It results that he can successfully get 3-shifts turn around time for severe-delivery-date lots with a payment equal to about 2-shifts line-cost.

A novel delivery management system using a new lot sampling scheduling (LSS) method has been developed. The method involves the concepts of "virtual line" and "marker lot," and the system consists of an on-line scheduler executing short-period scheduling for lot-tracking and an off-line scheduler executing long-period scheduling for delivery date simulation. The LSS method can hugely increase the maximum number of lots to simulate the delivery date and also control TAT more effectively compared to conventional dynamic scheduling. Lot progress is controlled by varying the resource allocation ratio for each virtual line. This method is effective for precise delivery date control of lots with various priorities in ASIC production or development lines.

A scalable and flexible ASIC CIM system distributed on UNIX workstations, ORCHARD , has been developed. It is designed from three viewpoints: (1) cost and TAT reduction in system construction, (2) flexibility in data management for quality control, and (3) precise and quick scheduling and effective lot tracking to control TAT for each lot. The concept of a "virtual machine" is introduced to connect equipment having various protocols to a host system. The virtual machine is automatically generated at an average automatic generation ratio of as high as 89%, which leads to a reduction in cost and TAT in system construction. Data for quality control is managed by changing flexibly the "data processing recipe." This recipe defines screen format, data collected from equipment, and data transfered from various databases. Precise scheduling of lots with various levels of priority is achieved by introducing a priority evaluation function, thereby reducing scheduling time to 1/20 that for manual scheduling.

We propose a method for configuring LSI manufacturing lines so that they can not only be used to manufacture low-cost LSIs in bulk quantities but also can be used to manufacture small lots with ultra-short TAT. This is achieved by adding a relatively small amount of single-wafer processing equipment to a existing conventional processing line, and therefore involves minimum investment.

The former experimental results have already shown that it is oxide films formed on contact surface causing the contact resistance to degrade in dc. breaking arcs for Ag and Pd materials. In order to understand the detailed information about it, the experiments are performed to break dc. inductive load at 20 V, 0.5 A and 1.0 A in nitrogen gas with different oxygen concentrations. The contact surface morphology and surface contamination are evaluated by SEM and AES, respectively. The tested results demonstrate that, for Ag contact, the severe oxidation occurs with increasing oxygen concentration, and the critical value of oxygen concentration is found to be about 10% and 5% in 0.5 A and 1.0 A, respectively, above those values the contact resistance degrades due to the oxide films formed on the contact surface, especially on the anode surface. While, for Pd contacts, a remarkable contact resistance degradation is not found even at 1.0 A in oxigen. Evidence shows that the arc duration, in particular the gaseous phase arc duration affects the anode oxidation, which in turn causes the significant fluctuation of contact resistance.

An on-line scheduler for ASIC manufacturing line management has been developed. The parameters in the schedule models and the dynamic priority curve in the schedule algorithm were adjusted to obtain schedules well-suited to practical ASIC line management and control. The scheduler is connected to the user interface control module of our ASIC CIM system. In order to facilitate on-line scheduling, we clarify the performance requirements of the computer used for the scheduler with respect to the line scale. Using a current EWS, the scheduler can easily make a one-day schedule for a small-scale line with an annual throughput of less than 1,000 lots within 10 minutes. To cope with larger-scale lines, the multiple scheduling method allows schedules to be produced quickly and efficiently. Therefore, the scheduler can respond flexibly to changes in production plan and line resources and the control delivery date of each lot.