A histogram is a common graphical descriptor to represent features of distribution of pixels in an image. However, for most of the applications that apply histograms, the time complexity of histogram construction is much higher than that of the other parts of the applications. Hence, column histograms had been presented to construct the local histogram in constant time. In order to increase its performance, this letter proposes a linked-list histogram to avoid generating empty bins, further using hash tables with bin entries to map pixels. Experimental results demonstrate the effectiveness of the proposed method and its superiority to the state-of-the-art method.

With the trend towards increasing number of cores, for example, 1000 cores, interconnection network in manycore chips has become the critical bottleneck for providing communication infrastructures among on-chip cores as well as to off-chip memory. However, conventional on-chip mesh topologies do not scale up well because remote cores are generally separated by too many hops due to the small-radix routers within these networks. Moreover, projected scaling of electrical processor-memory network appears unlikely to meet the enormous demand for memory bandwidth while satisfying stringent power budget. Fortunately, recent advances in 3D integration technology and silicon photonics have provided potential solutions to these challenges. In this paper, we propose a hybrid photonic burst-switched interconnection network for large-scale manycore processors. We embed an electric low-diameter flattened butterfly into 3D stacking layers using integer linear programming, which results in a scalable low-latency network for inter-core packets exchange. Furthermore, we use photonic burst switching (PBS) for processor-memory network. PBS is an adaptation of optical burst switching for chip-scale communication, which can significantly improve the power efficiency by leveraging sub-wavelength, bandwidth-efficient optical switching. Using our physically-accurate network-level simulation environment, we examined the system feasibility and performances. Simulation results show that our hybrid network achieves up to 25% of network latency reduction and up to 6 times energy savings, compared to conventional on-chip mesh network and optical circuit-switched memory access scheme.

Sound source localization is an essential technique in many applications, e.g., speech enhancement, speech capturing and human-robot interaction. However, the performance of traditional methods degrades in noisy or reverberant environments, and it is sensitive to the spatial location of sound source. To solve these problems, we propose a sound source localization framework based on bi-direction interaural matching filter (IMF) and decision weighting fusion. Firstly, bi-directional IMF is put forward to describe the difference between binaural signals in forward and backward directions, respectively. Then, a hybrid interaural matching filter (HIMF), which is obtained by the bi-direction IMF through decision weighting fusion, is used to alleviate the affection of sound locations on sound source localization. Finally, the cosine similarity between the HIMFs computed from the binaural audio and transfer functions is employed to measure the probability of the source location. Constructing the similarity for all the spatial directions as a matrix, we can determine the source location by Maximum A Posteriori (MAP) estimation. Compared with several state-of-the-art methods, experimental results indicate that HIMF is more robust in noisy environments.

In this paper, a novel hybrid technique for analyzing complex antennas around the coated object is proposed, which is termed as “iterative vector fields with Physical Optics (PO)”. A closed box is used to enclose the antennas and the complex field vectors on the box' surfaces can then be obtained using Huygens principle. The equivalent electromagnetic currents on Huygens surfaces are computed by Higher-order Method of Moments (HOB-MoM) and the fields scattered from the coated object are calculated by PO method. In addition, the parallel technique based on Message Passing Interface (MPI) and Scalable Linear Algebra Package (ScaLAPACK) is employed so as to accelerate the computation. Numerical examples are presented to validate and to show the effectiveness of the proposed method on solving the practical engineering problem.

Point spread function (PSF) estimation plays a paramount role in image deblurring processing, and traditionally it is solved by parameter estimation of a certain preassumed PSF shape model. In real life, the PSF shape is generally arbitrary and complicated, and thus it is assumed in this manuscript that a PSF may be decomposed as a weighted sum of a certain number of Gaussian kernels, with weight coefficients estimated in an alternating manner, and an l1 norm-based total variation (TVl1) algorithm is adopted to recover the latent image. Experiments show that the proposed method can achieve satisfactory performance on synthetic and realistic blurred images.

Ni nanodots (NDs) used as nano-scale top electrodes were formed on a 10-nm-thick Si-rich oxide (SiO$_{mathrm{x}}$)/Ni bottom electrode by exposing a 2-nm-thick Ni layer to remote H$_{2}$-plasma (H$_{2}$-RP) without external heating, and the resistance-switching behaviors of SiO$_{mathrm{x}}$ were investigated from current-voltage ( extit{I--V}) curves. Atomic force microscope (AFM) analyses confirmed the formation of electrically isolated Ni NDs as a result of surface migration and agglomeration of Ni atoms promoted by the surface recombination of H radicals. From local extit{I--V} measurements performed by contacting a single Ni ND as a top electrode with a Rh coated Si cantilever, a distinct uni-polar type resistance switching behavior was observed repeatedly despite an average contact area between the Ni ND and the SiO$_{mathrm{x}}$ as small as $sim$ 1.9 $ imes$ 10$^{-12}$cm$^{2}$. This local extit{I--V} measurement technique is quite a simple method to evaluate the size scalability of switching properties.

MapReduce still suffers from a problem known as skew, where load is unevenly distributed among tasks. Existing solutions follow a similar pattern that estimates the load of each task and then rebalances the load among tasks. However, these solutions often incur heavy overhead due to the load estimation and rebalancing. In this paper, we present DynamicAdjust, a dynamic resource adjustment technique for mitigating skew in MapReduce. Instead of rebalancing the load among tasks, DynamicAdjust adjusts resources dynamically for the tasks that need more computation, thereby accelerating these tasks. Through experiments using real MapReduce workloads on a 21-node Hadoop cluster, we show that DynamicAdjust can effectively mitigate the skew and speed up the job completion time by up to 37.27% compared to the native Hadoop YARN.

As the number of cores and the working sets of parallel workloads increase, shared L2 caches exhibit fewer misses than private L2 caches by making a better use of the total available cache capacity, but they induce higher overall L1 miss latencies because of the longer average distance between the requestor and the home node, and the potential congestions at certain nodes. We observed that there is a high probability that the target data of an L1 miss resides in the L1 cache of a neighbor node. In such cases, these long-distance accesses to the home nodes can be potentially avoided. In order to leverage the aforementioned property, we propose Bayesian Theory based Adaptive Proximity Data Accessing (APDA). In our proposal, we organize the multi-core into clusters of 2x2 nodes, and introduce the Proximity Data Prober (PDP) to detect whether an L1 miss can be served by one of the cluster L1 caches. Furthermore, we devise the Bayesian Decision Classifier (BDC) to adaptively select the remote L2 cache or the neighboring L1 node as the server according to the minimum miss cost. We evaluate this approach on a 64-node multi-core using SPLASH-2 and PARSEC benchmarks, and we find that the APDA can reduce the execution time by 20% and reduce the energy by 14% compared to a standard multi-core with a shared L2. The experimental results demonstrate that our proposal outperforms the up-to-date mechanisms, such as ASR, DCC and RNUCA.

A Bayesian technique was used to obtain point estimators for the parameters of a bivariate exponential distribution associated to a two-component parallel electronic system and a point estimator for the system reliability function.

This paper proposes a novel greedy algorithm, called Creditability-Estimation based Matching Pursuit (CEMP), for the compressed sensing signal recovery. As proved in the algorithm of Stagewise Orthogonal Matching Pursuit (StOMP), two Gaussian distributions are followed by the matched filter coefficients corresponding to and without corresponding to the actual support set of the original sparse signal, respectively. Therefore, the selection for each support point is interpreted as a process of hypothesis testing, and the preliminarily selected support set is supposed to consist of rejected atoms. A hard threshold, which is controlled by an input parameter, is used to implement the rejection. Because the Type I error may happen during the hypothesis testing, not all the rejected atoms are creditable to be the true support points. The creditability of each preliminarily selected support point is evaluated by a well-designed built-in mechanism, and the several most creditable ones are adaptively selected into the final support set without being controlled by any extra external parameters. Moreover, the proposed CEMP does not necessitate the sparsity level to be a priori control parameter in operation. In order to verify the performance of the proposed algorithm, Gaussian and Pulse Amplitude Modulation sparse signals are measured in the noiseless and noisy cases, and the experiments of the compressed sensing signal recoveries by several greedy algorithms including CEMP are implemented. The simulation results show the proposed CEMP can achieve the best performances of the recovery accuracy and robustness as a whole. Besides, the experiment of the compressed sensing image recovery shows that CEMP can recover the image with the highest Peak Signal to Noise Ratio (PSNR) and the best visual quality.

The paper demonstrates a novel two-peak negative differential resistance (NDR) circuit combining Si-based metal-oxide-semiconductor field-effect-transistor (MOS) and SiGe-based heterojunction bipolar transistor (HBT). Compared to the resonant-tunneling diode, MOS-HBT-NDR has two major advantages in our circuit design. One is that the fabrication of this MOS-HBT-NDR-based application can be fully implemented by the standard BiCMOS process. Another is that the peak current can be effectively adjusted by the controlled voltage. The peak-to-valley current ratio is about 4136 and 9.4 at the first and second peak respectively. It is very useful for circuit designers to consider the NDR-based applications.

Small cell networks have been promoted as an enabling solution to enhance indoor coverage and improve spectral efficiency. Users usually deploy small cells on-demand and pay no attention to global profile in residential areas or offices. The reduction of cell radius leads to dense deployment which brings intractable computation complexity for resource allocation. In this paper, we develop a semi-distributed resource allocation algorithm by dividing small cell networks into clusters with limited inter-cluster interference and selecting a reference cluster for interference estimation to reduce the coordination degree. Numerical results show that the proposed algorithm can maintain similar system performance while having low complexity and reduced information exchange overheads.

Currency is one of the important measurements of data quality. The main purpose of the study on data currency is to determine whether a given data item is up-to-date. Though there are already several works on determining data currency, all the proposed methods have limitations. Some works require timestamps of data items that are not always available, and others are based on certain currency rules that can only decide relevant currency and cannot express uncertain semantics. To overcome the limitations of the previous methods, this paper introduces a new approach for determining data currency based on uncertain currency rules. First, a class of uncertain currency rules is provided to infer the possible valid time for a given data item, and then based on the rules, data currency is formally defined. After that, a polynomial time algorithm for evaluating data currency is given based on the uncertain currency rules. Using real-life data sets, the effectiveness and efficiency of the proposed method are experimentally verified.

We have analyzed the reflection characteristic of a T junction composed of two parallel plate waveguides in which the one is the anisotropic plasma filled waveguide and the other is the exciting waveguide. The fields in two waveguides can be expanded by mode functions and the matching of the E and H fields at the junction in the Fourier transform leads to a linear simultaneous equation for the reflection coefficients. We solved the equation and obtained the reflection coefficients numerically.

A lossless data embedding method that inserts data in images in the spatial domain is proposed in this paper. Though a lossless data embedding method once distorts an original image to embed data into the image, the method restores the original image as well as extracts hidden data from the image in which the data are embedded. To guarantee the losslessness of data embedding, all pixel values after embedding must be in the dynamic range of pixels. Because the proposed method modifies some pixels to embed data and leaves other pixels as their original values in the spatial domain, it can easily keep all pixel values after embedding in the dynamic range of pixels. Thus, both the capacity and the image quality of generated images are simultaneously improved. Moreover, the proposed method uses only one parameter based on the statistics of pixel blocks to embed and extract data. By using this parameter, this method does not require any reference images to extract embedded data nor any memorization of the positions of pixels in which data are hidden to extract embedded data. In addition, the proposed method can control the capacity for hidden data and the quality of images conveying hidden data by controlling the only one parameter. Simulation results show the effectiveness of the proposed method; in particular, it offers images with superior image quality to conventional methods.

This paper presents a novel low-power register file based on adiabatic logic. The register file consists of a storage-cell array, address decoders, read/write control circuits, sense amplifiers, and read/write drivers. The storage-cell array is based on the conventional memory cell. All the circuits except the storage-cell array employ CPAL (complementary pass-transistor adiabatic logic) to recover the charge of large node capacitance on address decoders, bit-lines and word-lines in fully adiabatic manner. The minimization of energy consumption was investigated by choosing the optimal size of CPAL circuits for large load capacitance. The power consumption of the proposed adiabatic register file is significantly reduced because the energy transferred to the large capacitance buses is mostly recovered. The energy and functional simulations are performed using the net-list extracted from the layout. HSPICE simulation results indicate that the proposed register file attains energy savings of 65% to 85% as compared to the conventional CMOS implementation for clock rates ranging from 25 to 200 MHz.

A stabilized local oscillator is one of the key components for any radar system, especially for a Doppler radar in detecting slowly moving targets. Based on hybrid semiconductor/superconductor circuitry, the HTS local oscillator produces stable, low noise performance superior to that achieved with conventional technology. The device combines a high Q HTS sapphire cavity resonator (f=5.6 GHz) with a C-band low noise GsAs HEMT amplifier. The phase noise of the oscillator, measured by a HP 3048A noise measurement system, is -134 dBc/Hz at 10 kHz offset at 77 K.

In this letter, we propose a novel Uniformity-Approximated Histogram Equalization (UAHE) algorithm to enhance the image as well as to preserve the image features. First, the UAHE algorithm generates the image histogram and computes the average value of all bins as the histogram threshold. In order to approximate the uniform histogram, the bins of image histograms greater than the above threshold are clipped, and the subtracted counts are averaged and uniformly assigned to the remaining bins lower than the threshold. The approximated uniform histogram is then applied to generate the intensity transformation function for image contrast enhancement. Experimental results show that our algorithm achieves the maximum entropy as well as the feature similarity values for image contrast enhancement.

This paper presents method that offers the fast and accurate analysis of large-scale periodic array antennas by conjugate-gradient fast Fourier transform (CG-FFT) combined with an equivalent sub-array preconditioner. Method of moments (MoM) is used to discretize the electric field integral equation (EFIE) and form the impedance matrix equation. By properly dividing a large array into equivalent sub-blocks level by level, the impedance matrix becomes a structure of Three-level Block Toeplitz Matrices. The Three-level Block Toeplitz Matrices are further transformed to Circulant Matrix, whose multiplication with a vector can be rapidly implemented by one-dimension (1-D) fast Fourier transform (FFT). Thus, the conjugate-gradient fast Fourier transform (CG-FFT) is successfully applied to the analysis of a large-scale periodic dipole array by speeding up the matrix-vector multiplication in the iterative solver. Furthermore, an equivalent sub-array preconditioner is proposed to combine with the CG-FFT analysis to reduce iterative steps and the whole CPU-time of the iteration. Some numerical results are given to illustrate the high efficiency and accuracy of the present method.

Embedded systems are constrained by the available memory, and code-compression techniques address this issue by reducing the code size of application programs. The main challenge for the development of an effective code-compression technique is to reduce code size without affecting the overall system performance. Dictionary-based code-compression schemes are the most commonly used code-compression methods, because they can provide both good compression ratio and fast decompression. We propose an XOR-based reference scheme that can enhance the compression ratio on all the existing dictionary-based algorithms by changing the distribution of the symbols. Our approach works on all kinds of computer architecture with fixed length instructions, such as RISC or VLIW. Experiments show that our approach can further improve the compression ratio with nearly no hardware, performance, and power overheads.