We suggest a novel digitally-controlled SMPS using a high-resolution DPWM generator. In the proposed circuit, the duty ratio of the DPWM is determined by the voltage slope control of an internal capacitor using a pseudo relaxation-oscillation technique. This new control method has a simpler structure, and consumes less power compared to a conventional digitally-controlled SMPS. Therefore, the proposed circuit is able to operate at a high switching frequency (1 MHz10 MHz) obtained from a relatively low internal operating frequency (10 MHz100 MHz) with a small area. The maximum current of the core circuit is 2.7 mA, and the total current of the entire circuit, including the output buffer driver, is 15 mA at 10 MHz switching frequency. The proposed circuit is designed to supply a maximum 1A with maximum DPWM duty ratio of 90%. The output voltage ripple is 7 mV at 3.3 V output voltage. To verify the operation of the proposed circuit, we performed a simulation with Dongbu Hitek BCD 0.35 µm technology.

A novel high-speed and low-voltage CMOS level shifter circuit is proposed. The proposed circuit is suitable for block-level dynamic voltage and frequency scaling (DVFS) environment or multiple-clock and multiple-power-domain logic blocks. In order to achieve high performance in a chip consisting of logic blocks having different VDD voltages, the proposed circuit uses the circuit techniques to reduce the capacitive loading of input signals and to minimize the contention between pull-up and pull-down transistors through positive feedback loop. The techniques improve the slew rate of output signals, so that the level transient delay and duty distortions can be reduced. The proposed level up/down shifters are designed to operate over a wide range of voltage and frequency and verified with Berkeley's 65 nm CMOS model parameters, which can cover a voltage range from 0.6 to 1.6 V and at least frequency range up to 1000 MHz within 3% duty errors. Through simulation with Berkeley's 65 nm CMOS model parameters, the level shifter circuits can solve the duty distortion preventing them from high speed operation within the duty ratio error of 3% at 1 GHz. For verification through performance comparison with reported level shifts, the simulations are carried out with 0.35 µm CMOS technology, 0.13 µm IBM CMOS technology and Berkeley's 65 nm CMOS model parameters. The compared results show that delay time and duty ratio distortion are improved about 68% and 75%, respectively.