A sub-harmonic RF transmitter architecture with simultaneous power combination and carrier-leakage cancellation is proposed. It employs an 8-phase ring-type voltage controlled oscillator (VCO), sub-harmonic mixers, driver amplifiers, and a balun. A signal power is combined with its 180° phase-shifted signal through the balun. Simultaneously carrier-leakage generating in sub-harmonic mixers is canceled by its phase difference. The proposed transmitter achieved 1 dBm 1-dB output compression point (P-1dB) under 1.8 V supply and -40 dBm carrier-leakage in 5 GHz band.

A low-power switching method using a bootstrapping circuit is proposed for a high-speed output driver of transmitter. Compared with a conventional output driver, the proposed scheme employs only nMOSFETs to transmit data. The bootstrapping circuit ensures the proper switching of nMOSFET. The proposed scheme is simulated and fabricated using a 0.18 µm CMOS technology, showing 10.2% lower power consumption than a conventional switching driver at 2.5 Gb/s data rate.

A complete 4-level pulse amplitude modulation (4-PAM) serial link transceiver including a wide frequency range clock generator and clock data recovery (CDR) is proposed in this paper. A dual-loop architecture, consisting of a frequency locked loop (FLL) and a phase locked loop (PLL), is employed for the wide frequency range clocks. The generated clocks from the FLL (clock generator) and the PLL (CDR) are utilized for a transmitter clock and a receiver clock, respectively. Both FLL and PLL employ the identical voltage controlled oscillators consisting of ring-type delay-cells. To improve the frequency tuning range of the VCO, deep triode PMOS loads are utilized for each delay-cell, since the turn-on resistance of the deep triode PMOS varies substantially by the gate-voltage. As a result, fabricated in a 0.13-µm CMOS process, the proposed 4-PAM transceiver operates from 1.5 Gb/s to 9.7 Gb/s with a bit error rate of 10-12. At the maximum data-rate, the entire power dissipation of the transceiver is 254 mW, and the measured jitter of the recovered clock is 1.61 psrms.

This letter presents the design and analysis of phase noise optimization of a 4-GHz differential Colpitts voltage-controlled-oscillator (VCO). A low phase noise is achieved by a Colpitts oscillator and a VCO bias optimization using an amplitude control method. The measured phase noise is -134.8 dBc/Hz at 1.25 MHz offset frequency from 4 GHz operating frequency. The VCO is implemented using 0.24 µm SiGe BiCMOS process with integrated copper inductors. The wide VCO frequency range covers both PCS and IMT bands and draws about 15.9 mA from a 2.7 V power supply.

A 12 Gb/s 10-level pulse amplitude modulation (PAM) serial-link transmitter was implemented using a 0.18 µm CMOS process. The proposed 10-PAM transmitter achieves a channel efficiency of 4 bit/symbol by dual-mode amplitude modulations using 10 differential-mode levels and 3 common-mode levels. The measured maximum data-rate was 12 Gb/s over 0.7-m cable and 2-cm printed circuit board (PCB) traces. The entire transmitter consumes 432 mW such that the figure of merit of the transmitter is 36 pJ/bit. The present work demonstrates the greater channel efficiency of 4 bit/symbol than the currently reported multi-level PAM transmitters.