Two implementation schemes for a two-step SOVA (Soft Output Viterbi Algorithm) decoder are proposed and verified in a chip. One uses the combination of trace back (TB) logic to find the survivor state and double trace back logic to find the weighting factor of a two-step SOVA. The other is that the reliability values are divided by a scaling factor in order to compensate for the distortion brought by overestimating those values in SOVA. We introduced a fixed scaling factor of 0.25 or 0.33 for a rate 1/3 and designed an 8-state Turbo decoder with a 256-bit frame size to lower the reliability values. The implemented architecture of the two-step SOVA decoder allows important savings in area and high-speed processing compared with the one-step SOVA decoder using register exchange (RE) or trace-back (TB) method. The chip is fabricated using 0.65 µm gate array at Samsung Electronics and it shows higher SNR performance by 2 dB at the BER 10-4 than that of a two-step SOVA decoder without a scaling factor.

Fast and simple algorithm of a parity checker for a large residue numbers is presented. A new set of RNS moduli with 2r-(2l1) form for fast modular multiplication is proposed. The proposed RNS moduli has a large dynamic range for a large RNS number. The parity of a residue number can be checked by the Chinese remainder theorem (CRT). A CRT-based parity checker is simply organized by the Montgomery reduction method (MRM), implemented by using multipliers and the carry-save adder array. We present a fast parity checker with minimal hardware processed in three clock cycles for 32-bit RNS modulus set.

A second-order sigma-delta modulator with a 3-bit internal quantizer featuring a gain scaling of an internal ADC and a very simple internal DAC has been designed and implemented in a 0.8 µm double-poly double-metal CMOS process. We improved the performance of the modulator with the gain scaling of a 3-bit internal ADC and design of the internal error-free DAC with using simple logic gates. The specification of each component is determined for the modulator to have 14-bit resolution by time based modeling and the designed components satisfy the required specifications. The peak SNR of 87 dB and dynamic range of 87 dB were achieved at a clock rate of 2.816 MHz for 22 kHz baseband. The measured results show that the fabricated modulator lower SNR by 14 dB than that of the simulation due to the non-ideal input source and the disregarded error factors in the modeling such as the voltage variable capacitors etc.