We propose three effective approximate belief propagation decoders for polar codes using Maclaurin's series, piecewise linear function, and stepwise linear function. The proposed decoders have the better performance than that of existing approximate belief propagation polar decoders, min-sum decoder and normalized min-sum decoder, and almost the same performance with that of original belief propagation decoder. Moreover, the proposed decoders achieve such performance without any optimization process according to the code parameters and channel condition unlike normalized min-sum decoder, offset min-sum decoder, and their variants.

In this paper, we investigate how to obtain binary locally repairable codes (LRCs) with good locality and availability from binary Simplex codes. We first propose a Combination code having the generator matrix with all the columns of positive weights less than or equal to a given value. Such a code can be also obtained by puncturing all the columns of weights larger than a given value from a binary Simplex Code. We call by block-puncturing such puncturing method. Furthermore, we suggest a heuristic puncturing method, called subblock-puncturing, that punctures a few more columns of the largest weight from the Combination code. We determine the minimum distance, locality, availability, joint information locality, joint information availability of Combination codes in closed-form. We also demonstrate the optimality of the proposed codes with certain choices of parameters in terms of some well-known bounds.

In this paper, we examine the locality property of the original Fractional Repetition (FR) codes and propose two constructions for FR codes with better locality. For this, we first derive the capacity of the FR codes with locality 2, that is the maximum size of the file that can be stored. Construction 1 generates an FR code with repetition degree 2 and locality 2. This code is optimal in the sense of achieving the capacity we derived. Construction 2 generates an FR code with repetition degree 3 and locality 2 based on 4-regular graphs with girth g. This code is also optimal in the same sense.

This paper proposes a new FeRAM design style based on grounded-plate PMOS-gate (GPPG) cell structure. A GPPG cell consists of a PMOS access transistor and a ferroelectric capacitor. Its plate is grounded. The proposed scheme employs three novel operating methods: 1) VDD precharged bitline, 2) negative-voltage wordline technique and 3) negative-pulse restore. Because this configuration doesn't need the on-pitch plate control circuitry, it is effective in realizing cost-effective chip sizes. Implementation of a 2.5-V, 2-Mb FeRAM prototype design in a 0.5-µm technology shows a cell array efficiency of 57%, an access time of 85 ns and an active current of 12 mA, respectively.