We propose a new compaction problem that allows layout elements to have many shape possibilities. The objective of the problem is to find not only positions but also shapes of layout elements. We present an efficient method to solve the problem--compaction with shape optimization. This method simplifies the problem by considering the optimization of shapes only for the layout elements on a critical path. The layout is compacted step by step while optimizing the shapes of layout elements. Another importance of this compaction technique is that it makes layout to be "recyclable" for other set of device parameters. The experimental examples, which attempt shape optimization and recycle of analog layout, confirms the importance and efficiency of our method.

In the floorplan design problem, soft blocks can take various rectilinear shapes. The conventional floorplanning methods, however, restrict their shapes only to rectangle. As a result, waste area often remains in the layout. Some floorplanning methods have been developed to handle rectilinear hard blocks, however, no floorplanning methods have been developed to optimize rectilinear soft blocks. In this paper, we propose a floorplanning method which places rectilinear soft blocks. The advantages of the method are reducing both waste area and wire length. We present Separate-Rejoin method which efficiently forms rectilinear shapes for soft blocks. The result is obtained quickly because the method is based on the slicing structure in spite of handling rectilinear block. Thus, our method is suitable for practical use in terms of layout area, wire length and processing time. We applied our method to a benchmark example and an industrial data. For the benchmark example, our method reduces waste area by 25% and wire length by 13% in comparison with the conventional rectangular soft block approach.

The Bach compiler is a behavioral synthesis tool, which synthesizes RT-level circuits from behavioral descriptions written in the Bach C language. It shortens the design period of LSI and helps designers concentrate on algorithm design and refinement. In this paper, we propose methods for optimizing the area and performance of algorithms described in Bach C. In our experiments, we optimized a Viterbi decoder algorithm using our proposed methods and synthesized the circuit using the Bach compiler. The conclusion is that the circuit produced using Bach is both smaller and faster than the hand-coded register transfer level (RTL) design. This proves that the Bach compiler produces high-quality results and the Bach C language is effective for describing the behavior of hardware at a high-level.

In this paper, we propose a cell synthesis method for a Salicide process. Our method utilizes the local interconnect between adjacent transistors, which is available in some Salicide processes, and optimizes the transistor placement of a cell considering both area and the number of local interconnects. In this way we reduce the number of metal wires and contacts. The circuit model is not restricted to conventional series-parallel CMOS logic, and our method enables us to synthesize CMOS pass-transistor circuits. Experimental results show that our method uses the local interconnect effectively, and optimizes both cell area and metal wire length.