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It was more than 10 years ago that the first map navigation system, as an example of invehicle information system, has appeared in the market in Japan. Today's navigation system has been improved to the level that the latest system has 10 micro-processors, 7 MBytes of memories, and 4 GBytes of external data storage for map database. From the viewpoint of the automobile driver, there are still some problems with the system. Major problems in general are a lack of traffic information, better human interface, and a need for cost-reduction. The introduction of application specific ICs (ASICs) is expected to make systems smaller, costless, and give higher speed response. Today's in-vehicle information systems are reviewed function by function to discover what functions need to be implemented into ASICs for future systems, what ASICs will be required, and what technology has to be developed. It is concluded that more integration technology is expected including high parformance CPUs, large capacity memories, interface circuits, and some analog circuits such as DA converter. To develop this technology, some, major problems such as power consumption, number of input/output signals, as well as design aid and process technology are pointed out.
Takuya WADATSUMI Kohei KAWAI Rikuu HASEGAWA Kikuo MURAMATSU Hiromu HASEGAWA Takuya SAWADA Takahito FUKUSHIMA Hisashi KONDO Takuji MIKI Makoto NAGATA
This paper presents on-chip characterization of electrostatic discharge (ESD) impacts applied on the Si-substrate backside of a flip-chip mounted integrated circuit (FC-IC) chip. An FC-IC chip has an open backside and there is a threat of reliability problems and malfunctions caused by the backside ESD. We prepared a test FC-IC chip and measured Si-substrate voltage fluctuations on its frontside by an on-chip monitor (OCM) circuit. The voltage surges as large as 200mV were observed on the frontside when a 200-V ESD gun was irradiated through a 5kΩ contact resistor on the backside of a 350μm thick Si substrate. The distribution of voltage heights was experimentally measured at 20 on-chip locations among thinned Si substrates up to 40μm, and also explained in full-system level simulation of backside ESD impacts with the equivalent models of ESD-gun operation and FC-IC chip assembly.