This paper describes a newly developed automatic direction control scheme for bi-directional bus repeaters that uses dynamic collaborative driving techniques. Repeater directions are rapidly determined by detecting the direction of control signal propagation through an additional control signal line that is driven by dynamic collaborative drivers. Application to an on-chip peripheral bus reduces control circuit transistor counts by about 75% and the number of control signal lines by about 50% without loss of speed. Experimental results for a 0.18-µm CMOS implementation indicate that the proposed scheme is four times faster than a conventional scheme with no bi-directional bus repeaters.

In practice, even a well-trained neural machine translation (NMT) model can still make biased inferences on the training set due to distribution shifts. For the human learning process, if we can not reproduce something correctly after learning it multiple times, we consider it to be more difficult. Likewise, a training example causing a large discrepancy between inference and reference implies higher learning difficulty for the MT model. Therefore, we propose to adopt the inference discrepancy of each training example as the difficulty criterion, and according to which rank training examples from easy to hard. In this way, a trained model can guide the curriculum learning process of an initial model identical to itself. We put forward an analogy to this training scheme as guiding the learning process of a curriculum NMT model by a pretrained vanilla model. In this paper, we assess the effectiveness of the proposed training scheme and take an insight into the influence of translation direction, evaluation metrics and different curriculum schedules. Experimental results on translation benchmarks WMT14 English ⇒ German, WMT17 Chinese ⇒ English and Multitarget TED Talks Task (MTTT) English ⇔ German, English ⇔ Chinese, English ⇔ Russian demonstrate that our proposed method consistently improves the translation performance against the advanced Transformer baseline.

This paper presents a design of a new multiple-valued matching VLSI processor for high-speed reasoning. It is useful in the application for real-time rule-based systems with large knowledge bases which are programmable. In order to realize high-speed reasoning, the matching VLSI processor can perform the fully parallel pattern matching between an input data and rules. On the based of direct multiple-valued encoding of each attribute in an input data and rules, pattern matching can be described by using only a programmable delta literal. Moreover, the programmable delta literal circuit can be easily implemented using two kinds of floating-gate MOS devices whose threshold voltages are controllable. In fact, it is demonstrated that four kinds of threshold voltages in a practical floating-gate MOS device can be easily programmable by appropriately controlling the gate, the drain and the source voltage. Finally, the inference time of the quaternary matching VLSI processor with 256 rules and conflict resolution circuits is estimated at about 360 (ns), and the chip area is reduced to about 30 percent, in comparison with the equivalent binary implementation.