Reducing communication complexity is a viable approach to multilevel logic synthesis. A communication complexity based approach was proposed previously. In the previous works, only disjoint input decomposition was considered. However, for certain types of circuits, the circuit size can be reduced by using overlapped decomposition. In this paper, we consider overlapped decompositions. Some design issues for overlapped decompositions such as detecting globals" and deriving subfunctions are addressed. Moreover, the Decomposition Don't Cares (DDC) is considered for improving the decomposed results. By using these techniques together, the area and delay of circuits can be further minimized.