In this paper, a sub-optimal Rake receiver combined with a Wiener Filter is investigated for use in an indoor environment. Inner-Chip-interference is dominant when the application is indoors, so the inner-chip-interference rejection function becomes critical for the receiver. Pilot symbols in each slot are used for channel estimation and weight calculation of Rake combining through Wiener Filter. Compared to conventional combining which uses maximum ratio combining, Wiener combining using IRC (Interference rejection combining) achieves better ICI (Inner-chip-Interference) rejection. This paper clarified that the sub optimal Rake receiver using Wiener Filter is 4 dB better than the conventional Rake receiver under the indoor application.

With VLSI design development, the increasingly severe power problem requests to minimize clock routing wirelength so that both power consumption and power supply noise can be alleviated. In contrast to most of traditional works that handle this problem only in clock routing, we propose to navigate standard cell register placement to locations that enable further less clock routing wirelength and power. To minimize adverse impacts to conventional cell placement goals such as signal net wirelength and critical path delay, the register placement is carried out in the context of a quadratic placement. The proposed technique is particularly effective for the recently popular prescribed skew clock routing. Experiments on benchmark circuits show encouraging results.

The sharpness of the roll-off response of bandpass filters is a major concern for wireless communication systems. Bandpass filters with attenuation poles provide sharp roll-off. This paper investigates the performance of a ceramic comb-line filter with attenuation pole resonators (APRs), and studies the effects of the attenuation pole resonators on the filter response. The presented APRs are improved versions of previous ones and they are modeled here. The obtained results show that the length of APRs can be miniaturized via the loading capacitance. The resultant volume is about 400 mm3, which is very small comparing to coaxial type filters with the same attenuation rate in the stopband. With attenuation pole resonators added, skirt attenuation is greatly improved. Narrow bandwidth bandpass filters with attenuation poles in the stopband are designed and tested. Two designed examples demonstrate the flexibility of the attenuation pole resonator in the filter configuration. Experiments show good agreement with simulation results.

This paper presents a maximum likelihood (ML) identification and restoration method for noisy blurred images. The unitary discrete sine transform (DST) is employed to decouple the large order spatial state-space representation of the noisy blurred image into a bank of one-dimensional real state-space scalar subsystems. By assuming that the noises are Gaussian distributed processes, the maximum likelihood estimation technique using the expectation-maximization (EM) algorithm is developed to jointly identify the blurring functions, the image model parameters and the noise variances. In order to improve the computational efficiency, the conventional Kalman smoother is incorporated to give the estimates. The identification process also yields the estimates of transformed image data, from which the original image is restored by the inverse DST. The experimental results show the effectiveness of the proposed method and its superiority over the recently proposed spatial domain DFT-based methods.

GaAs MMICs (Monolithic Microwave Integrated Circuits) reliability is a critical part of the overall reliability of the thermal solution in semiconductor devices. With MMICs reliability improved, GaAs MMICs failure rates will reach levels which are impractical to measure with conventional methods in the near future. This letter proposes a methodology to predict the GaAs MMICs reliability by combining empirical and statistical methods based on zero-failure GaAs MMICs life testing data. Besides, we investigate the effect of accelerated factors on MMICs degradation and make a comparison between the Weibull and lognormal distributions. The method has been used in the reliability evaluation of GaAs MMICs successfully.

This letter presents a novel weighted reliability-based (WRB) algorithm for decoding low-density parity-check (LDPC) codes. Viewing the well-known normalized min sum (NMS) algorithm as reliability-based, the WRB algorithm can be seen as a simplified version of the NMS algorithm. Unlike the NMS algorithm, the WRB algorithm does not update the soft information sent between the variable nodes and check nodes, which greatly reduces the decoding complexity. For finite geometry LDPC codes with larger row redundancy and column weights, simulation results show that the WRB algorithm almost matches the error performance of the NMS algorithm.

As the function of a system getting more complex, IP (Intellectual Property) reusing is the trend of system design style. Designers need to evaluate the performance and features of every candidate IP block that can be used in their design, while IP providers hope to keep the structure of their IP blocks a secret. An IP level power model is a model that takes only the primary input statistics as parameters and does not reveal any information about the sizes of the transistors or the structure of the circuit. This paper proposes a new method for constructing power model that is suitable for IP level circuit blocks. It is a nominal point selection method for power models based on power sensitivities. By analyzing the relationship between the dynamic power consumption of CMOS circuits and their input signal statistics, a guideline of selecting the nominal point is proposed. From our analysis, the first nominal point is selected to minimize the average estimation error and two other nominal points are selected to minimize the maximum estimation error. Our experimental results on a number of benchmark circuits show the effectiveness of the proposed method. Average estimation accuracy within 5.78% of transistor level simulations is achieved. The proposed method can be applied to build a system level power estimation environment without revealing the contents of the IP blocks inside. Thereby, it is a promising method for IP level power model construction.