In this research, we investigated the effect of Hf inter layer and chemical oxide on Si(100) substrate on the ferroelectric undoped HfO2 deposition. In case with 1 nm-thick Hf inter layer, equivalent oxide thickness (EOT) was decreased from 6.0 to 4.8 nm for 10 nm-thick HfO2 with decreasing annealing temperature. In case with 0.5 nm-thick chemical oxide, EOT was decreased from 3.9 to 3.6 nm in MFS diodes for 5 nm-thick HfO2. The MFSFET was fabricated with 10 nm-thick HfO2 utilizing Hf inter layer. The subthreshold swing was improved from 240 mV/dec. to 120 mV/dec. and saturation mobility was increased from 70 cm2/(Vs) to 140 cm2/(Vs) by inserting Hf inter layer.

In this research, we investigated the threshold voltage (VTH) control by partial polarization of metal-ferroelectric-semiconductor field-effect transistors (MFSFETs) with 5 nm-thick nondoped HfO2 gate insulator utilizing Kr-plasma sputtering for Pt gate electrode deposition. The remnant polarization (2Pr) of 7.2 μC/cm2 was realized by Kr-plasma sputtering for Pt gate electrode deposition. The memory window (MW) of 0.58 V was realized by the pulse amplitude and width of -5/5 V, 100 ms. Furthermore, the VTH of MFSFET was controllable by program/erase (P/E) input pulse even with the pulse width below 100 ns which may be caused by the reduction of leakage current with decreasing plasma damage.

In this research, we investigated the metal-ferroelectric-semiconductor field-effect transistors (MFSFETs) with 5nm thick nondoped HfO2 gate insulator by decreasing the sputtering power for Pt gate electrode deposition. The leakage current was effectively reduced to 2.6×10-8A/cm2 at the voltage of -1.5V by the sputtering power of 40W for Pt electrode deposition. Furthermore, the memory window (MW) of 0.53V and retention time over 10 years were realized.