Stereo depth estimation has become an attractive topic in the computer vision field. Although various algorithms strive to optimize the speed and the precision of estimation, the energy cost of a system is also an essential metric for an embedded system. Among these various algorithms, Semi-Global Matching (SGM) has been a popular choice for some real-world applications because of its accuracy-and-speed balance. However, its power consumption makes it difficult to be applied to an embedded system. Thus, we propose a robust stereo matching system, RT-libSGM, working on the Xilinx Field-Programmable Gate Array (FPGA) platforms. The dedicated design of each module optimizes the speed of the entire system while ensuring the flexibility of the system structure. Through an evaluation on a Zynq FPGA board called M-KUBOS, RT-libSGM achieves state-of-the-art performance with lower power consumption. Compared with the benchmark design (libSGM) working on the Tegra X2 GPU, RT-libSGM runs more than 2× faster at a much lower energy cost.

Degradation of metal-oxide-semiconductor field-effect transistors (MOSFETs) reliability such as the relative transconductance reduction by plasma exposure is evaluated. The linear region peak transconductance (gm) decreases with antenna ratio (exposed antenna area/gate area) due to the plasma-induced Si-SiO2 interface state generation. The Si-SiO2 interface-related gm reduction which is defined as (gm0gm)/gm, where gm0 is the initial value of gm, decreases as the gate oxide thickness decreases. It is also found that the decreasing amount of gm depends on the conduction current from the plasma. The correlation between the (gm0gm)/gm and the plasma-induced reduction of charge-to-breakdown of the gate oxide with a constant current stress (ΔQBD) is observed, and the result shows that the gm reduction of nMOSFET during the plasma process is severe to the plasma-induced damage compared with the gate oxide breakdown.

Automobile companies have been trying to replace side mirrors of cars with small cameras for reducing air resistance. It enables us to apply some image processing to improve the quality of the image. Contrast Limited Adaptive Histogram Equalization (CLAHE) is one of such techniques to improve the quality of the image for the side mirror camera, which requires a large computation performance. Here, an implementation method of CLAHE on a low-end FPGA board by high-level synthesis is proposed. CLAHE has two main processing parts: cumulative distribution function (CDF) generation, and bilinear interpolation. During the CDF generation, the effect of increasing loop initiation interval can be greatly reduced by placing multiple Processing Elements (PEs). and during the interpolation, latency and BRAM usage were reduced by revising how to hold CDF and calculation method. Finally, by connecting each module with streaming interfaces, using data flow pragmas, overlapping processing, and hiding data transfer, our HLS implementation achieved a comparable result to that of HDL. We parameterized the components of the algorithm so that the number of tiles and the size of the image can be easily changed. The source code for this research can be downloaded from https://github.com/kokihonda/fpga_clahe.