As an enhancement of the state-of-the-art solutions, a high-throughput architecture of a decoder for structured LDPC codes is presented in this paper. Thanks to the peculiar code definition and to the envisaged architecture featuring memory paging, the decoder is very flexible, and the support of different code rates is achieved with no significant hardware overhead. A top-down design flow of a real decoder is reported, starting from the analysis of the system performance in finite-precision arithmetic, up to the VLSI implementation details of the elementary modules. The synthesis of the whole decoder on 0.18µm standard cells CMOS technology showed remarkable performances: small implementation loss (0.2dB down to BER = 10-8), low latency (less than 6.0µs), high useful throughput (up to 940Mbps) and low complexity (about 375 Kgates).

In this paper a low-complexity and high-resolution algorithm to estimate the magnitude of complex numbers is presented. Starting from a review of previous art, the new algorithm has been derived to improve precision performance without any penalty in hardware complexity. As a case example, a semi-custom VLSI implementation for 10 bit 2's complement input data has been performed. A mean square error and mean error performance improvement of nearly one order of magnitude has been demonstrated for an hardware complexity increase of roughly 34% with respect to previously presented solutions.

This paper presents a new modulation scheme for Very-High Speed Digital Subscriber Lines (VDSL) modem, featuring a Multi-Code Multi-Carrier Code Division Multiple Access (MC2-CDMA) modulation. The system takes advantage from both the CDMA modulation and the Multi-Carrier transmission, and furthermore the channel throughput is increased adopting a multi-code approach. Starting from an overview of this novel scheme, encompassing the transmitter, channel and receiver description, a brief review of the equalization techniques is also considered and a proper bit-loading algorithm is derived to find out the achievable overall channel rate. The aim of this paper, besides introducing this novel scheme, is to demonstrate its suitability for a VDSL environment, where the achievable channel rate represents a real challenge. By means of a further optimisation, a general improvement of the system performance with respect to the standardized Discrete Multi Tone (DMT) modulation is also demonstrated.