Timing vernier (i.e., digital-to-time converter) is a key component of the pin-electronics circuit board installed in automated digital-VLSI test equipment, and it is used to create fine delays of less than one-cycle time of a clock signal. This paper presents a new on-the-fly (timing-) jitter suppression technique which makes it possible to use low-power plain-CMOS-logic-based timing verniers. Using a power-compensation line installed at the poststage of the digitally variable delay line, we make every pulse (used as a timing signal) consume a fixed amount of electric energy independent of the required delay amount. Since the power load of intrapowerlines is kept constantly, the jitter increase in the situation of changing the required delay amount on the fly is suppressed. On the basis of the concept, a 10-ns span, 125-MHz timing-vernier macro was designed and fabricated with a CMOS process for logic VLSIs. Every macro installed in a real-time timing-signal generator VLSI achieved the required timing resolution of 31.25ps with a linearity error within 15ps. The on-the-fly jitter was successfully suppressed to a random jitter level (<26ps p-p).

For wireless communication, a low-voltage monolithic LC-tank CMOS voltage-controlled-oscillator (VCO) is developed with 0.2-µm fully-depleted silicon-on-insulator (SOI) CMOS process technology. The VCO features a double-tuning technique to achieve a wide tuning range with lateral p-n junction varactors. The VCO has the following features at the supply voltage of 1.5 V: (1) Output frequency range from 1.07 GHz to 1.36 GHz, (2) Third-harmonic below -37 dBc, and (3) Phase noise of -120 dBc/Hz at 1 MHz offset frequency.

To reduce the power dissipation of the receiver in accordance with the intensity of the received signal, we developed the first intra-symbol intermittent (ISI) radio-frequency (RF) front end with 0.35-µm CMOS technology. In the demodulation mechanism, the RF output of the low-noise amplifier (LNA) is down-converted to an intermediate frequency (IF) by the mixer, and the LNA and mixer operate synchronously and intermittently within the length of a single symbol. Because the time-averaged power consumption is proportional to the operating time, the demodulation can be performed with low power by making the total operating time short. We experimentally demonstrate that demodulation (BPSK: 9.6 kbps) is properly achieved with the operating-time ratio of 12%. This ISI operation of the RF front end is enabled by a newly devised fast-transition LNA and mixer. A theoretical analysis of aliasing noise reveals that RF ISI operation is more useful than current-control with continuous operation and that an operating-time ratio of 10% is optimal.