We propose a class of multiple input multiple output (MIMO) systems using the transmit diversity pre-combining (TDPC) scheme, assuming perfect channel state information (CSI) at a transmitter. In such a class of systems, each transmitter antenna is weighted independently according to the channel condition so that the Euclidean distance between the closest symbols at a receiver could be maximized under a total transmit power constraint. We also introduce an effective space-time trellis code (STTC) for the proposed class of MIMO systems. From computer simulations, we see that incorporating both the TDPC scheme and the proposed STTC outperforms the MIMO system using only the TDPC scheme and the conventional STTC-MIMO system.

In general, message passing multiprocessors suffer from communication overhead and shared memory multiprocessors suffer from memory contention. Also, data I/O overhead limits performance. In particular, computer vision tasks that require massive computation are strongly affected by these disadvantages. This paper proposes new parallel architectures for computer vision, a Flexibly (Tightly/Loosely) Coupled Multiprocessor (FCM) and a Flexibly Coupled Hypercube Multiprocessor (FCHM) to alleviate these problems. FCM and FCHM have a variable address space memory in which a set of neighboring memory modules can be merged into a shared memory by a dynamically partitionable topology. FCM and FCHM are based on two different topologies: reconfigurable bus and hypercube. The proposed architectures are quantitatively analyzed using computational models and parallel vision algorithms are simulated on FCM and FCHM using the Intel's Personal SuperComputer (iPSC), a hypercube multiprocessor, showing significant performance improvements over that of iPSC.

We propose a new orthogonal frequency division multiplexing transmission scheme using orthogonal code multiplexing. This scheme makes all modulation symbols have the same reliability even in a frequency selective fading channel, through a distributed transmission of each symbol over the whole effective subcarriers using a distinct orthogonal code. As an appropriate set of orthogonal multiplexing codes, we use the set of discrete Fourier transform code sequences that hold the orthogonality irrespective of the length. Using this set, we also can greatly reduce the peak-to-average-power ratio (PAR) of the resulting signal. Simulation results show that the proposed scheme can significantly reduce the required signal-to-noise ratio at a given bit error rate over the existing schemes. The scheme can maintain the PAR within a reasonable range of about 6 dB even up to 512 subcarriers and works well even with PAR clipping of 1.5 dB.

This paper proposes efficient DSP instructions and their hardware architecture for the Viterbi algorithm. The implementation of the Viterbi algorithm on a DSP chip has been attracting more interest for its flexibility, programmability, etc. The proposed architecture can reduce the Trace Back (TB) latency and can support various wireless communication standards. The proposed instructions perform the Add Compare Select (ACS) and TB operations in parallel and the architecture has special hardware, called the Offset Calculation Unit (OCU), which automatically calculates data addresses for acceleration of the trellis butterfly computations. When the constraint length K is 5, the proposed architecture can reduce the decoding cycles about 17% compared with Carmel DSP and about 45% compared with TMS320C55x.