In practical applications of digital filters it is more realistic to treat multiplier coefficients as finite intervals than restricting them to infinite or very long word-length representations. However, this can not be done it the frequency response performance under interval assumption is difficult to analyze. In this paper, it is proved that stable lattice allpass filters possess bounded continuous phase response when lattice parameters vary in bounded intervals. It is shown that sharp bounds on the interval phase response can be computed easily at an arbitrary frequency using a simple recursive procedure. Application of this property to the problem of finite word-length lattice allpass filter design is also discussed. By formulating this problem as an interval design it is possible to solve it efficiently independent of the number system used to represent multiplier coefficients.

Voltage follower is one of the most useful building blocks in analog circuits. This paper proposes a voltage follower composed of a complementary pair of p-channel MOS(PMOS) and n-channel MOS (NMOS) differential amplifiers which operates under low power supply. The proposed circuit has a rail-to-rail dynamic range by combining complementary differential amplifiers.

In multidimensional signal sampling, the orthogonal sampling scheme is the simplest one and is employed in various applications, while a non-orthogonal sampling scheme is its alternative candidate. The latter sampling scheme is used mainly in application where the reduction of the sampling rate is important. In three-dimensional (3-D) signal processing, there are two typical sampling schemes which belong to the non-orthogonal samplings; one is face-centered cubic sampling (FCCS) and the other is body-centered cubic sampling (BCCS). This paper proposes a new design method for 3-D band-limiting FIR filters required for such non-orthogonal sampling schemes. The proposed method employs the McClellan transformation technique. Unlike the usual 3-D McClellan transformation, however, the proposed design method uses 2-D prototype filters and 2-D transformation filters to obtain 3-D FIR filters. First, 3-D general sampling theory is discussed and the two types of typical non-orthogonal sampling schemes, FCCS and BCCS, are explained. Then, the proposed design method of 3-D bandlimiting filters for these sampling schemes is explained and an effective implementation of the designed filters is discussed briefly. Finally, design examples are given and the proposed method is compared with other method to show the effectiveness of our methos.

This paper proposes a rail-to-rail OTA. By adding a signal decomposing circuit at the input of given OTAs that have a limited input voltage range, a rail-to-rail OTA is obtained. Each decomposed input voltage signal is converted to a current signal by an OTA and each output current of OTAs is summed to obtain a linear output signal. Since the input signal is decomposed into small magnitude voltage signals, the OTAs used to the voltage-current conversion do not require a wide input-range and any OTA can be used to realize a rail-to-rail input voltage range OTA. HSPICE simulations are performed to verify the validity of the proposed method.

This paper proposes a jitter tolerant continuous-time sigma-delta A-D converter structure as well as its design method. This method transforms a conventionally designed sigma-delta A-D converter into a jitter tolerant one. Jitter tolerance is provided by the modified feedback signal paths and a consequently inserted digital LPF. This method is applicable independently of a system order and the other specifications.

This paper proposes a design technique for 3-D non-separable QMF banks with Face-Centered Cubic Sampling (FCCS) and Body-Centered Cubic Sampling (BCCS). In the proposed technique, 2-D McClellan transformation is applied to a suitably designed 2-D prototype QMF to obtain 3-D QMFs. The design examples given in this paper demonstrate advantages of the proposed method.

It is shown that two-dimensional linear phase FIR digital filters with various shapes of frequency response can be designed and realized as modular array structures free of multiplier coefficients. The design can be performed by judicious selection of two low order linear phase transfer functions to be used at each module as kernel filters. Regular interconnection of the modules in L rows and K columns conditioned with boundary coefficients 1, 0 and 1/2 results in higher order digital filters. The kernels should be chosen appropriately to, first, generate the desired shape of frequency response characteristic and, second, lend themselves to multiplierless realization. When these two requirements are satisfied, the frequency response can be refined to possess narrower transition bands by adding additional rows and columns. General properties of the frequency response of the array are investigated resulting in Theorems that serve as valuable tools towards appropriate selection of the kernels. Several design examples are given. The array structures enjoy several favorable features. Specifically, regularity and lack of multiplier coefficients makes it suitable for high-speed systolic VLSI implementation. Computational complexity of the structure is also studied.

This paper presents an automatic synthesis method of active analog circuits that uses evolutionary search and employs some topological features of analog integrated circuits. Our system firstly generates a set of circuits at random, and then evolves their topologies and device sizing to fit an environment which is formed by the fitness function translated from the electrical specifications of the circuit. Therefore expert knowledge about circuit topologies and sizing are not needed. The capability of this method is demonstrated through experiments of automatic synthesis of CMOS operational amplifiers.

In this paper, a new design idea for class A CMOS second generation current conveyor (CCII) is discussed. Based on the proposed idea, a new architecture for a CMOS CCII is presented. The proposed circuit is free from body effect and provides high performance in terms of input resistance and transfer gain errors. HSPICE simulation results also have shown remarkable performance over the wide bandwidth.

FIR digital filters composed of parallel multiple subfilters are proposed. A binary expression of an input signal is decomposed into multiple shorter words, which drive the subfilters having different length. The output error is evaluated by mean squared and maximum spectra. A fast algorithm is also proposed to determine optimal filter lengths and coefficients of subfilters. Many examples confirm that the proposed filters generate smaller output errors than conventional filters under the condition of specified number of multiplications and additions in filter operations. Further, multiplier and adder structures (MAS) to perform the operations of the proposed filters are also presented. The number of gates used in the proposed MAS and its critical path are estimated. The effectiveness of the proposed MAS is confirmed.

A mapping circuit in order to have a wider input dynamic range is proposed. MOSFET's connecting between power supply lines are employed to construct the mapping circuit. SPICE simulation is shown to evaluate the proposed circuits. With the proposed mapping circuit, two-MOSFET subtractor has a rail-to-rail input voltage. As an application, an OTA consisting of subtractors is realized by employing the proposed mapping circuits to have a rail-to-rail input voltage range.

This paper discusses a new simultaneous design method of both magnitude and phase of IIR digital filters. It is inherently a nonlinear problem to approximate the magnitude and phase of an IIR digital filter simultaneously. In this paper, however, such a nonlinear problem is converted into a linear one by vector rotation method and solved by the linear programming (LP) technique. As a result our method requires no initial guesses for any type of filter specifications. A stable digital filter is designed which approximately satisfies the linearity of the phase in the pass band and the given attenuation in the stop band. The design examples given in this paper shows the usefulness of the proposing method.

A new approach for generating a system model from its input-output data is presented. The model is approximated as a linear combination of simple basis functions. The number of basis functions is kept as small as possible to prevent over-fitting and to make the model efficiently computable. Based on these conditions, genetic programming is employed for the generation and selection of the appropriate basis. Since the obtained model can be expressed in simple mathematical expressions, it is suitable for using the model as a macro or behavior model in system level simulation. Experimental results are shown.

In this paper, is shown an approach to realize leapfrog structures obtained from proto-type passive RLC ladder filters using current differencing buffered amplifiers (CDBA) as active elements. The use of the CDBA's provides advantages that the realization procedure is simplified and the number of active components required is reduced. The approach is quite suitable for the realization of band-pass ladder filters, which generally requires a complicated structure to simulate LC series and/or parallel resonant branches by the conventional opamp-based leapfrog filters. A simple circuit configuration of the CDBA suitable for high frequency and low power supply voltage applications is also presented. As design examples, a fifth-order Butterworth lowpass ladder filter and a sixth-order Chebyshev bandpass ladder filter are designed. The effectiveness and the correctness of the proposed approach and the characteristics of the proposed filters are verified and examined through computer simulation.

An automated synthesis for analog computational circuits in transistor-level configuration is presented. A cell-based structure is introduced to place moderate constraints on the MOSFET circuit topology. Even though each cell has a simple structure that consists of one current path with four transistors, common analog building blocks can be implemented using combinations of the cells. A genetic algorithm is applied to search circuit topologies and transistor sizes that satisfy given specifications. Synthesis capabilities are demonstrated through examples of three types of computational circuits; absolute value, squaring, and cubing functions by using computer simulations and real hardware.

This paper presents an automated design of linear and non-linear differential analog circuits accelerated by reuse of genetic operations. The system first synthesizes circuits using pairs of simplified MOSFET model. During the evolutionary process, genetic operations that improve circuit characteristics are stored in a database and reused to effectively obtain a better circuit. Simplified elements in a generated circuit are replaced by MOSFETs and optimization of the transistor size is performed using an optimizer available in market if necessary. The capability of this method is demonstrated through experiments of synthesis of a differential voltage amplifier, a circuit having cube-law characteristic in differential mode and square-law characteristic in common-mode, and a dB-linear VGA (Variable Gain Amplifier). The results show the reuse of genetic operations accelerates the synthesis and success rate becomes 100%.

This letter proposes a simulation of an input part of an LCR filter. The proposed method used voltage followers as an active element. As an example, a realization of a 3 MHz third-order maximally-flat filter is presented.

An automated analog circuit synthesis based on reuse of topological features of 'prototype circuits' is proposed. The prototype circuits are designed by humans and suggested to the synthesis system as hints of configurations of new analog circuits to be synthesized by the system. The connections of elements in analog circuits are not generally systematic, but they would have some similarities to a circuit which has similar behaviors or functionalities. In the proposed process, the information on circuit connections is stored as sub-circuits extracted from the prototype circuits. And then, genetic algorithm is used to search for an optimum combination of the sub-circuits that achieves the desired electronic specifications. The combinations of sub-circuits are performed with a novel technique where the terminals of the sub-circuits are shared. The capabilities of the proposed method are demonstrated through an example of the synthesis.

An integrator is quite a suitable active element for high-speed filters. The effect of its excess phase shifts, however, is severe in the case of high-Q filter realization. The deterioration due to the excess phase shifts cannot be avoided when only integrators are used as frequency-dependent elements like in leapfrog realization. This paper describes a design of second-order high-speed and high-Q filters with low sensitivity to excess phase shifts of integrators by adding a passive RC circuit. The proposed method can drastically reduce the effect due to the undesirable pole of an integrator, which is the cause of the excess phase shifts, compared to conventional filters using only integrators. As an example, a fourth-order bandpass filter with 5-MHz center frequency and Q=25 is implemented by the proposed method on a monolithic chip. The results obtained here show quite good agreement with the theoretical values. This demonstrates effectiveness of the proposed method and feasibility of high-speed and high-Q filters on a monolithic chip.

A building block for widening an input range under low power-supply voltages is proposed and the block is used in a popular linearization technique for voltage-to-current converters. The block employs two MOSFETs each of which actively works when and only when the other is in cutoff region. Accurate level shift circuits for the control of the MOSFETs enable such exclusive operation. Simulation results show that the complementary MOSFETs perform as an equivalent MOSFET without any cutoff region. It is also confirmed that the novel linear voltage-to-current converter is effective for not only a wide input range but also low-power consumption.