A double-capacitor phase error compensation configuration is proposed for Gm-C and MOSFET-C filters. The use of two capacitors enables the effective compensation capacitance to track with the tuning resistance, thereby making it more effective over a wider frequency tuning range as compared to the conventional single-capacitor configuration. Simulations of 5th-order Chebyshev filters in a 0.18 µm CMOS process with more than one octave tuning range were carried out to demonstrate the viability of the proposed double-capacitor configuration for both Gm-C and MOSFET-C filters.

A compact OTA suitable for low-voltage active-RC and MOSFET-C filters is presented. The input stage of the OTA utilises the resistive tail-biased differential amplifier and the output stage relies upon the feed-forward class AB technique with common-mode rejection capability that incurs no penalty on transconductance/bias-current efficiency. Analysis on the achievable peak voltage swing of the OTA when employed in filters is given. Simulation results of a 0.5-V 100-kHz elliptic 5th-order filter based on the OTA's in a 2-V 0.18 µm CMOS process indicate the differential peak voltage as large as 0.42 Vp (84% of the supply voltage) at 1% THD with the SFDR of 60 dB and the total power consumption of 50 µW.

The sub-threshold R-MOSFET resistor structure which enables tuning range extension below the threshold voltage in the MOSFET with moderate to weak inversion operation is analyzed in detail. The principal operation of the sub-threshold resistor is briefly described. The analysis of its characteristic based on approximations of a general MOS equation valid for all regions is given along with discussion on design implication and consideration. Experiments and simulations are provided to validate the theoretical analysis and design, and to verify the feasibility at a supply voltage as low as 0.5 V using a low-threshold devices in a 1.8-V 0.18 µm CMOS process.

A compact OTA suitable for low-voltage active-RC and MOSFET-C filters is presented. The input stage of the OTA utilises the NMOS pseudo-differential amplifier with PMOS active load. The output stage relies upon the dual-mode feed-forward class-AB technique (based on an inverter-type transconductor) with common-mode rejection capability that incurs no penalty on transconductance/bias-current efficiency. Simulation results of a 0.5-V 100-kHz 5th-order Chebyshev filter based on the proposed OTA in a 0.18 µm CMOS process indicate SNR and SFDR of 68 dB and 63 dB (at 50 kHz+55 kHz) respectively. The filter consumes total power consumption of 60 µW.