Abstract machine modelling is a technique used frequently in developing the retargetable compilers. By translating the abstract machine operations into target machine instructions, we can construct retargetable compilers. However, such a technique will cause two problems. First, the code produced by the compilers is inefficient. Next, in order to emit the efficient code, the compilation time is too long. In view of these two disadvantages, we apply PO (peephole optimizer) in our retargetable compilers to do code optimization. Peephole optimizer searches for the adjacent instruction candidates in the intermediate code, and then replaces them with equivalent instructions of less cost. Furthermore, the peephole description table consists of simple tree-rewriting rules which are easily retargeted into different machines. At the same time, we have proposed a simple peephole pattern matching algorithm to reduce the peephole pattern matching time. The experiment indicates that the machine code generated by our compiler runs faster than that by GNU c compiler (gcc).

By treating each different output pattern as a state, we propose a low power architecture for pipelined circuits using bipartition. It is possible that the output of a pipelined circuit transit mainly among some of different states. If some few states dominate most of the time, we could partition the combinational portion of a pipelined circuit into two blocks: one that contains the few states with high activity is small and the other that contains the remainder with low activity is big. The original pipelined circuit is bipartitioned into two individual pipelined circuits. An additional combination logic block is introduced to control which of the two partitioned blocks to work. Power reduction is based on the observation that most time the small block is at work and the big one is at idle. In order to minimize the power consumption of this architecture, we present an algorithm that can improve the efficiency of this additional control block. Experiments with MCNC benchmarks show high percentage of power saving by using our new architecture for low power pipelined circuit design.