A CMOS design to achieve high drivability is examined for lower power supply voltage in 0.5 µm ULSI. The design consists of two points. (1) A very narrow (50 nm) sidewall is used to achieve high drivability and also to obtain hot-carrier-reliability. (2) A retrograded channel profile with NMOS and PMOS is designed to achieve high drivability and also to reduce short channel effect. It is shown that the propagation delay times (tpd) of a unloaded Inverter and a loaded 2-way NAND gate are improved 30% with the newly designed CMOS, compared with the conventionally designed CMOS. It is also proved that the tpd keeps the scaling trend of the previous-5 V-era even in 3.3 V-era by adapting the newly designed CMOS. Moreover, 7.1 ns multiplication time of 1616-bit multiplier is obtained under 0.5 µm design rule.

We report on the spurious suppression effect in low-microwave power transmitters by high temperature superconducting (HTS) bandpass filters (BPFs) which are promising for devices requiring BPFs with high-frequency selectivity. Some of the major issues on the power BPFs with HTS planar circuits for wireless communication applications are reviewed. As a case study for the HTS filter and its spurious suppression effect, this paper describes an example of the measured power spectrum density (PSD) on the suppression effect by one of our developed power BPFs with YBCO films for the 5 GHz band. It was designed with equivalent cascade resonators of 16 poles. We demonstrated the effect by HTS power filter in a power amplifier for the 5 GHz band.