This paper presents the architecture and design of the video CODEC circuit that can compress and reconstruct 4:2:2 color VGA video images in real time. Our circuit is based on two-dimensional DWT and inter-frame compression technique. For low-power real-time operation, we modified the traditional Mallat's sub-band coding method to reduce the amount of computation and memory access required in two-dimensional DWT. We also incorporated inter-frame compression technique into our CODEC circuit to enhance the compression capability. To avoid an intensive computation required in motion detection, we encoded only the macro blocks in the current frame which are different from those in the same location of the previous frame to exploit the fact that the background image does not change much in DVR system. We fabricated the CODEC chip using 0.35 µm 3.3 V CMOS standard cell process and applied it to the 16-channel DVR security system.

We devised an efficient architecture of deblocking filter and implemented the circuit with 15,400 logic gates and a 16032 dual-port SRAM using 0.25 µm standard cell technology. This circuit can process 88 image frames with 1,280720 pixels per second at 166 MHz. Our circuit requires smaller number of accesses to the external memory than other approaches and hence causes less bus traffic in the SoC design platform.