The application of pulse-doped GaAs MESFET's to a power amplifier module is discussed in this paper. The epitaxial layer structure was redesigned to have a dual pulse-doped structure for power applications, achieving a sufficient gate-drain brakdown voltage with excellent linearity. The measured load-pull characteristics of the redesigned device for the minimum power consumption design was presented. This device was shown to have almost twice the power-added efficiency of a conventional ion-implanted GaAs MESFET. Two kinds of power amplifiers were designed and fabricated, achieving Pout of 28.6 dBm at IM3 of -40 dBc with Pdc of 8 W and Pout of 33.0 dBm at IM3 of -40 dBc with Pdc of 32 W, respectively.

A monolithic four-stage low-noise amplifier (LNA) was successfully demonstrated for direct broadcast satellite (DBS) down-converters using 0.3 µm gate pulse-doped GaAs MESFET's This paper presents the design and test results of the LNA. The key feature of the research is a detailed demonstration of the difference between a noise figure of the four-stage LNA and an optimal noise figure of an employed FET with simulation and experiments. This LNA shows VSWR's of below 1.5: 1 as well as a noise figure of 1.1 dB and a gain of 28 dB at 12 GHz. To the best of our knowledge, it is the lowest noise figure reported so far in 12 GHz-band MMIC amplifiers. In the power characteristics, a 1 dB compression point (P1dB) of 10 dBm and a third order intercept point (IP3) of 19 dBm were shown.

An InGaP/GaAs composite channel has been proposed in order to improve the electron transport properties of InGaP for high power device applications. The electron mobility and velocity are increased due to the contribution of high mobility GaAs. Although the composite channel FET shows higher transconductance and drain current than those of the InGaP single channel FET, the breakdown voltage is nearly the same. The composite channel FET delivered output power of 0.6 W/mm with power added efficiency of 46.2% under 17 V operation at 1.9 GHz.

A detabase system that provides step-by-step guidance for LSI failure analysts has been developed. This system has three main functions: database, navigator, and chip tracking. The datebase stores failure analysis information such as analysis method and failure mechanisms including image data. It also stores conditions and results of each analysis step and decisions to proceeds to the next analysis step. With 2000 failure analysis cases, data retrieval takes 6.6 seconds, a table containing 20 photos is presented in 6.5 seconds, and a different set of data can be displayed in 0.6 seconds. The navigator displays a standard analysis procedure illustrated in flow charts.The chip tracking shows where the particular chip is and what analysis it is undergoing, which is useful for the situation where many chips are simultaneously analyzed. Thus, this system has good enough functions of analysis procedure management and performance of quick data access to make failure analysis easier and more successful.

A practical EB-testing-pad method, that enables higher observability of multilevel wiring LSIs without any increase of chip size, has been evaluated by using actual 0.25-µm SIMOX/CMOS devices. First, an 80k-gate logic LSI with testing pads was developed, and it was proved that observability improves from 17% to 87%. Next, two kinds of gate-chain TEGs (test element groups), with and without testing pads was developed to investigate the influence of testing pads on gate delay. It was found that the circuit delay increase due to the pads is very small, less than 2.7%. It was also found that capacitances from neighboring wires will increase only by at most 3% due to the testing pads. Thus, the testing pad method has been proved to be extremely effective in improving observability without any overhead in design.