An efficient data transmission interface for VLSI systems, Multi-Bit Parallel Code Division Multiple Access (MB/P-CDMA) interface, has been designed with 0.35 µm CMOS technology. The proposed interface achieves 1.12 Gb/s data rate (80 MHz, 8 bit bus) using multi-bit transmission at each clock per transmitter. The proposed CDMA interface ensures higher speed operation than conventional interface even in noisy environments. Each of the transmitters and receivers occupies the die area of 290 360 µm2 and 240 280 µm2, respectively.

Wired CDMA interface with adaptivity for interconnect capacitances is designed to receive transmitted data even under a wide variety of connection topologies. The variable gain amplifier (VGA) is one of key circuit blocks to realize the adaptivity for interconnect capacitances. The system level numerical simulations derive the VGA specifications that the required VGA gain range is from 0.37 to 2.0, which can be realized easily using a multiple-differential-pair technique.