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Toshihiro MATSUDA Ryuichi MINAMI Akira KANAMORI Hideyuki IWATA Takashi OHZONE Shinya YAMAMOTO Takashi IHARA Shigeki NAKAJIMA
A pure CMOS threshold-voltage reference (VTR) circuit achieves temperature (T) coefficient of 5 µV/(T = -60+100) and supply voltage (VDD) sensitivity of 0.1 mV/V (VDD = 35 V). A combination of subthreshold current, linear current and saturation current in n-MOSFETs provides a small voltage and temperature dependence. Three different regions in I-V characteristics of MOSFETs generate a constant VTR based on threshold voltage at 0 K. A feedback scheme from the reference output to gates of n-MOSFETs extremely stabilizes the output. The circuit consists of only 17 MOSFETs and its simple scheme saves the die area, which is 0.18 mm2 in the TEG (Test Element Group) chip fabricated by 1.2 µm n-well CMOS process.