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Takao YAMAZAKI Yoshihito KONDO Sayuri IGOTA Seiichiro IWASE
We have developed a method to automatically generate a multi-input-adder circuit for an irregular array of partial products. "FASTOOL," an FIR Filter Automatic Synthesis TOOL for an HDL design environment, is proposed for use with this method and with conventional filter coefficient design programs. Filter design from specifications to the structure of Verilog-HDL has been automated. It is possible for a system designer to quickly perform filter LSI optimization by balancing cost and performance.
Hisao OIKAWA Takao YAMAZAKI Hidetoshi KIMURA
Estimating the macroscopic demand for telephones is essential to long-term planning construction of telecommunication networks facilities. Although there are several useful forecast equations, they need some types and/or vast amounts of data that are sometimes unavailable, especially in developing countries. This paper presents a sophisticated telephone demand estimation technique that is based on the demands of residential and business users. It uses several parameters to estimate the increase in telephone demand. A simplified equation is also presented that is a function of only one parameter: normalized gross domestic product (GDP) per capita. This simplified equation is shown to be useful by using data for more than ten countries.
Akihiko HASHIGUCHI Masuyoshi KUROKAWA Ken'ichiro NAKAMURA Hiroshi OKUDA Koji AOYAMA Mitsuharu OHKI Katsunori SENO Ichiro KUMATA Masatoshi AIKAWA Hirokazu HANAKI Takao YAMAZAKI Mitsuo SONEDA Seiichiro IWASE
A programmable DSP with linear array architecture for real-time video processing is reported. It achieves a processing rate of 5. 4 GOPS and 81GB/s memory bandwidth using Dual Sense Amplifier architecture. A low-power-supply pipeline decreases power consumption and a time shared bit-line reduces chip area. It has 4320 processor elements and a 1. 1 Mbit 3-port memory. The DSP can be applied to HDTV signals with its 75 MHz peak I/O rate. Sufficient programmability is provided to execute video format conversion such as image size conversion and Y/C separation, and picture quality improvement such as noise reduction and image enhancement. The chip was fabricated using 0. 4 µm CMOS triple metal technology with a 15. 12 mm 14. 95 mm die. It operates at 50 MHz and consumes 0. 53 W/GOPS at 3. 3 V.