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[Author] Takeo MIYATA(2hit)

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  • Development and Evaluation of the SDMA Test Bed for PHS in the Field

    Yoshiharu DOI  Jun KITAKADO  Tadayoshi ITO  Takeo MIYATA  Seigo NAKAO  Takeo OHGANE  Yasutaka OGAWA  

     
    PAPER

      Vol:
    E86-B No:12
      Page(s):
    3433-3440

    Many carriers are introducing multi-media services to satisfy customer demands for these services. In order to provide such services, carrier must increase their system capacity. It is well known that space division multiple access (SDMA) improves system capacity and is compatible with existing access systems. In order to evaluate the performance of SDMA, we developed an SDMA test bed. The test bed maintains the personal handy phone systems (PHS). The PHS adopts time division multiple access (TDMA). Aiming to compare the performance of SDMA and TDMA using the same analog hardware, the SDMA test bed employs a software-defined radio (SDR) technique. This paper shows the outline and performance of the test bed. The results of laboratory tests indicate that the bit error rate (BER) of the test bed operated in the SDMA mode at under 10-3 when the carrier-tointerference ratio (CIR) was larger than approximately -22 dB. Antenna patterns measured in an anechoic chamber show that the SDMA test bed produces correct antenna patterns when there are three desired signals and one interference signal. The results of the four field tests confirm that the test bed operated while two-multiplex SDMA mode doubled of the traffic and decreased the interference level as compared with the TDMA mode. Furthermore, the test bed operated while threemultiplex SDMA mode improves the traffic about 2.4 to 2.7 times. The SDMA test bed decreased the impact of the adjusted TDMA base station (BS). Therefore, we confirmed that the SDMA improves system capacity without any degradation.

  • A Floating-Point A/D Converter with Self-Calibration

    Goichi OOTOMO  Kousuke TSUKAMOTO  Takeshi WATAHIKI  Takeo MIYATA  

     
    PAPER-Software Systems

      Vol:
    E71-E No:12
      Page(s):
    1303-1309

    This paper describes an A/D converter for signal processing applications which has a floating point format. This converter has been implemented using CMOS switches, an operational amplifier, a comparator, a binary weighted capacitor-array, and D/A converter for calibration. A 13-bit accuracy has been achieved with the self-calibration technique although the capacitor-array used has a 9-bit accuracy. Also other errors like stray capacitances, charge injection of the CMOS switches etc. are compensated by calibration circuit.

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