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Isamu KAJITANI Masaya IWATA Nobuyuki OTSU Tetsuya HIGUCHI
This paper presents a new reconfigurable hardware paradigm, called evolvable hardware (EHW), and its application to the biomedical engineering problem of an artificial hand controller. Evolvable hardware is based on the idea of combining a reconfigurable hardware device with an artificial intelligence robust search technique called genetic algorithms (GAs) to execute reconfiguration autonomously. The first version of the EHW chip was designed in 1998, and this paper describes the latest improvements to the EHW chip, as well as outlining its architecture and the hardware implementation of the GA operations. Execution speed for genetic operations is shown to be about 38.7 times faster with the hardware implementation than with software program running on an AMD Athlon processor (1.2GHz). As an application of the EHW chip, this paper introduces a controller for a multi-functional prosthetic-hand, and presents experimental data in which a practical myoelectric pattern classification rate of 97.8% was achieved through the application of the EHW chip.
Yuji KASAI Kiyoshi MIYASHITA Hidenori SAKANASHI Eiichi TAKAHASHI Masaya IWATA Masahiro MURAKAWA Kiyoshi WATANABE Yukihiro UEDA Kaoru TAKASUKA Tetsuya HIGUCHI
This paper proposes the combination of adjustable architecture and parameter optimization software, employing a method based on artificial intelligence (AI), to realize an image rejection mixer (IRM) that can enhance its image rejection ratio within a short period of time. The main components of the IRM are 6 Gilbert-cell multipliers. The tail current of each multiplier is adjusted by the optimization software, and the gain and phase characteristics are optimized. This adjustment is conventionally extremely difficult because the 6 tail currents to be adjusted simultaneously are mutually interdependent. In order to execute this adjustment efficiently, we employed a Genetic Algorithm (GA) that is a robust search algorithm that can find optimal parameter settings in a short time. We have successfully developed an IRM chip that has a performance of 71 dB and is suitable for single-chip integration with WCDMA applications.