We have proposed the high-density triangular parallel wire channel MOSFET on an SOI substrate and demonstrated the suppressed short channel effects by simulation and experiment. In this device structure, the fabrication process is fully compatible with the planar MOSFET process and is much less complicated than other non-planer device structures including gate-all-around (GAA) and double-gate SOI MOSFETs. In addition, our fabrication process makes it possible to double the wire density resulting in the higher current drive. The three-dimensional simulation results show that the proposed triangular wire channel MOSFET has better short channel characteristics than single-gate and double-gate SOI MOSFETs. The fabricated triangular parallel wire channel MOSFETs show better subthreshold characteristics and less drain induced barrier lowering (DIBL) than the single-gate SOI MOSFETs.

The device design of future nanoscale MOSFETs is reviewed. Major challenges in the design of the nanometer MOSFETs and the possible solutions are discussed. In this paper, special emphasis is placed on the combination of new transistor structures that suppress the short channel effect and on back-gate voltage control that suppresses the characteristics variations. Two new device architectures, variable-body-factor FD SOI MOSFET and multigate MOSFET with low aspect ratio, have been proposed and their advantages are discussed.