Finding DC operating points of nonlinear circuits is an important and difficult task. The Newton-Raphson method adopted in the SPICE-like simulators often fails to converge to a solution. To overcome this convergence problem, homotopy methods have been studied from various viewpoints. However, most previous studies are mainly focused on the bipolar transistor circuits and no paper presents the global convergence theorems of homotopy methods for MOS transistor circuits. Moreover, due to the improvements and advantages of MOS transistor technologies, extending the homotopy methods to MOS transistor circuits becomes more and more necessary and important. This paper proposes two nonlinear homotopy methods for MOS transistor circuits and proves the global convergence theorems for the proposed MOS nonlinear homotopy method II. Numerical examples show that both of the two proposed homotopy methods for MOS transistor circuits are more effective for finding DC operating points than the conventional MOS homotopy method and they are also capable of finding DC operating points for large-scale circuits.

A PN junction current model for advanced MOSFETs is proposed and implemented into HiSIM2, a complete surface-potential-based MOSFET model. The model includes forward diode currents and reverse diode currents, and requires a total of 13 model parameters covering all bias conditions. Model simulation results reproduce measurements for different device geometries over a wide range of bias and temperature values.

An energy management circuit is proposed for self-powered ubiquitous sensor modules using vibration-based energy. With the proposed circuit, the sensor modules work with low duty cycle operation. Moreover, a two-tank circuit as a part of the energy management circuit is utilized to solve the problem that the average power density of ambient energy always varies with time while the power consumption of the sensor modules is constant and larger than it. In addition, the long start-up time problem is also avoided with the timing control of the proposed energy management circuit. The CMOS implementation and silicon verification results of the proposed circuit are also presented. Its validity is further confirmed with a vibration-based energy generation. The sensor module is used to supervise the vibration of machines and transfer the vibration signal discontinuously. A piezoelectric element acts as the vibration-to-electricity converter to realize battery-free operation.

Simple closed-form expressions for efficiently calculating on-chip interconnect capacitances are presented. The formulas are expressed with second-order polynomial functions which do not include exponential functions. The runtime of the proposed formulas is about 2-10 times faster than those of existing formulas. The root mean square (RMS) errors of the proposed formulas are within 1.5%, 1.3%, 3.1%, and 4.6% of the results obtained by a field solver for structures with one line above a ground plane, one line between ground planes, three lines above a ground plane, and three lines between ground planes, respectively. The proposed formulas are also superior in accuracy to existing formulas.

Recently, the compound element pseudo transient analysis, CEPTA, method is regarded as an efficient practical method to find DC operating points of nonlinear circuits when the Newton-Raphson method fails. In the previous CEPTA method, an effective SPICE3 implementation algorithm was proposed without expanding the Jacobian matrix. However the limitation of step size was not well considered. Thus, the non-convergence problem occurs and the simulation efficiency is still a big challenge for current LSI nonlinear cicuits, especially for some practical large-scale circuits. Therefore, in this paper, we propose a new SPICE3 implementation algorithm and an embedding algorithm, which is where to insert the pseudo capacitors, for the CEPTA method. The proposed implementation algorithm has no limitation for step size and can significantly improve simulation efficiency. Considering the existence of various types of circuits, we extend some possible embedding positions. Numerical examples demonstrate the improvement of simulation efficiency and convergence performance.

In general, a corner model with best- and worst-case delay conditions is used in static timing analysis (STA). The best- and worst-case delays of a stage are defined as the fastest and slowest delays from a cell input to the next cell input. In this paper, we present a methodology for determining the parameters that yield the best- and worst-case delays when interconnect structural parameters have the minimum and maximum values with process variations. We also present analysis results of our circuit model using the methodology. The min and max conditions for the time constant are found to be (+Δw, +Δt, +Δh) & (-Δw, -Δt, -Δh), respectively. Here, +Δ or -Δ means the max or min corner value of each parameter variation, where w is the width, t is the interconnect thickness, and h is the height. Best and worst conditions for delay time are as follows: 1) given a circuit with an optimum driver, dense interconnects, and small branch capacitance, the best and worst conditions are respectively (-Δw, +Δt, +Δh) & (+Δw, +Δt, -Δh), 2) given driver and/or via resistances that are higher than the interconnect resistance, dense interconnects, and small branch capacitance, they are (-Δw, -Δt, +Δh) & (+Δw, +Δt, -Δh), and 3) for other conditions, they are (+Δw, +Δt, +Δh) & (-Δw, -Δt, -Δh). Moreover, if there must be only one condition each for the best- and worst-case delays, they are (+Δw, +Δt, +Δh) & (-Δw, -Δt, -Δh).

Path following circuits (PFC's) are circuits for solving nonlinear problems on the circuit simulator SPICE. In the method of PFC's, formulas of numerical methods are described by circuits, which are solved by SPICE. Using PFC's, numerical analysis without programming is possible, and various techniques implemented in SPICE will make the numerical analysis very efficient. In this paper, we apply the PFC's of the homotopy method to various nonlinear problems (excluding circuit analysis) where the homotopy method is proven to be globally convergent; namely, we apply the method to fixed-point problems, linear programming problems, and nonlinear programming problems. This approach may give a new possibility to the fields of applied mathematics and operations research. Moreover, this approach makes SPICE applicable to a broader class of scientific problems.

Finding DC operating points of nonlinear circuits is an important problem in circuit simulation. The Newton-Raphson method employed in SPICE-like simulators often fails to converge to a solution. To overcome this convergence problem, homotopy methods have been studied from various viewpoints. There are several types of homotopy methods, one of which succeeded in solving bipolar analog circuits with more than 20000 elements with the theoretical guarantee of global convergence. In this paper, we propose an improved version of the homotopy method that can find DC operating points of practical nonlinear circuits smoothly and efficiently. Numerical examples show the effectiveness of the proposed method.

This paper proposes a 12-bit 3.7-MS/s pipelined A/D Converter based on the novel capacitor mismatch calibration technique. The conventional stage is improved to an algorithmic circuit involving charge summing, capacitors' exchange and charge redistribution, simply through introducing some extra switches into the analog circuit. This proposed ADC obtains the linearity beyond the accuracy of the capacitor match and verifies the validity of reducing the nonlinear error from the capacitor mismatch to the second order without additional power dissipation through the novel capacitor mismatch calibration technique. It is processed in 0.5 µm CMOS technology. The transistor-level simulation results show that 72.6 dB SNDR, 78.5 dB SFDR are obtained for a 2 V Vpp 159.144 kHz sine input sampled at 3.7 MS/s. The whole power dissipation of this ADC is 33.4 mW at the power supply of 5 V.

Gate delay evaluation is always a vital concern for high-performance digital VLSI designs. As the feature size of VLSIs decreases to the nano-meter region, the work to obtain an accurate gate delay value becomes more difficult and time consuming than ever. The conventional methods usually use iterative algorithms to ensure the accuracy of the effective capacitance Ceff, which is usually used to compute the gate delay with interconnect loads and to capture the output signal shape of the real gate response. Accordingly, the efficiency is sacrificed. In this paper, an accurate and efficient approach is proposed for gate delay estimation. With the linear relationship of gate output time points and Ceff, a polynomial approximation is used to make the nonlinear effective capacitance equation be solved without iterative method. Compared to the conventional methods, the proposed method improves the efficiency of gate delay calculation. Meanwhile, experimental results show that the proposed method is in good agreement with SPICE results and the average error is 2.8%.

Recently, an efficient algorithm has been proposed for finding all solutions of systems of nonlinear equations using inverses of approximate Jacobian matrices. In this letter, an effective technique is proposed for improving the computational efficiency of the algorithm with a little bit of computational effort.

In this paper, a nanopower supply-insensitive complementary metal-oxide-semiconductor (CMOS) unit threshold voltage (Vth) extractor circuit is proposed. It meets the contemporary industry demand for portable devices that operate with very low power consumption and small output sensitivity. An α times Vth (αVth) extractor is also described, in which α varies continuously. Both incremental and decremental αVth voltages are obtained. A post-layout simulation results using HSPICE with CMOS 0.18um process show that the proposed unit Vth extractor consumes 265nW of power given a 1.6V power supply. Sensitivity to temperature is 0.022%/°C ranging from 0°C to 100°C. Sensitivity to supply voltage is 0.027%/V.

An adaptive time-step control method is proposed for the damped pseudo-transient analysis (DPTA) method. The new method is based on the idea of switched evolution/relaxation (SER), which can automatically adapt the step size for different circuit states. Considering the number of iterations needed for the convergence of Newton-Raphson (NR) method and the states in previous steps, the proposed method can automatically optimize the time-step size. Using numerical examples, the new method is proven to improve robustness, simulation efficiency, and the convergence of DPTA for solving nonlinear DC circuit equations.

The compound element pseudo-transient analysis (PTA) algorithm is an effective practical method for finding the DC operating point when the Newton-Raphson method fails. It is able to effectively prevent from the oscillation problems compared with conventional PTA algorithms. In this paper, an effective SPICE3 implementation method for the compound element PTA algorithm is proposed. It has the characteristic of not expanding the Jacobian matrix and not changing the Jacobian matrix structure when the pseudo-transient numerical simulation is being done. Thus a high simulation efficiency is guaranteed. The ability of the proposed SPICE3 implementation to avoid the oscillation problems and the simulation efficiency are demonstrated by examples.

In this paper we propose a novel and efficient method for the optimization of the power/ground (P/G) network in VLSI circuit layouts with reliability constraints. Previous algorithms in the P/G network sizing used the sequence-of-linear-programming (SLP) algorithm to solve the nonlinear optimization problems. However the transformation from nonlinear network to linear subnetwork is not optimal enough. Our new method is inspired by the biological evolution and use the grid-genetic-algorithm (GGA) to solve the optimization problem. Experimental results show that new P/G network sizes are smaller than previous algorithms, as the fittest survival in the nature. Another significant advance is that GGA method can be applied for all P/G network problems because it can get the results directly no matter whether these problems are linear or not. Thus GGA can be adopted in the transient behavior of the P/G network sizing in the future, which recently faces on the obstacles in the solution of the complex nonlinear problems.

Finding DC operating points of transistor circuits is an important and difficult task. The Newton-Raphson method adopted in SPICE-like simulators often fails to converge to a solution. To overcome this convergence problem, homotopy methods have been studied from various viewpoints. For efficiency of globally convergent homotopy methods, it is important to give an appropriate initial solution as a starting point. However, there are few studies concerning such initial solution algorithms. In this paper, initial solution problems in homotopy methods are discussed, and an effective initial solution algorithm is proposed for globally convergent homotopy methods, which finds DC operating points of transistor circuits efficiently. Numerical examples using practical transistor circuits show the effectiveness of the proposed algorithm.

In deep submicron designs, predicting gate delays with interconnect load is a noteworthy work for Static Timing Analysis (STA). The effective capacitance Ceff concept and the Thevenin model that replaces the gate with a linear resistor and a voltage source are usually used to calculate the delay of gate with interconnect load. In conventional methods, it is not considered that the charges transferred into interconnect load and Ceff in the Thevenin model are not equal. The charge difference between interconnect load and Ceff has the large influence to the accuracy of computing Ceff. In this paper, an advanced effective capacitance model is proposed to consider the above problem in the Thevenin model, where the influence of the charge difference is modeled as one part of the effective capacitance to compute the gate delay. Experimental results show a significant improvement in accuracy when the charge difference between interconnect load and Ceff is considered.

Accurate estimating or measuring the intake manifold absolute pressure plays an important role in automobile engine control. In order to achieve the real-time estimation of the absolute pressure, the high accuracy and high speed processing ability are required for automobile engine control systems. Therefore, in this paper, an analog method is discussed and a fully integrated analog circuit is proposed to simulate automobile intake systems. Furthermore, a novel behavioral macromodeling is proposed for the analog circuit design. With the analog circuit, the intake manifold absolute pressure, which plays an important role for the effective automobile engine control, can be accurately estimated or measured in real time.

In deep submicron designs, predicting gate slews and delays for interconnect loads is vitally important for Static Timing Analysis (STA). The effective capacitance Ceff concept is usually used to calculate the gate delay of interconnect loads. Many Ceff algorithms have been proposed to compute gate delay of interconnect loads. However, less work has been done to develop a Ceff algorithm which can accurately predict gate slew. In this paper, we propose a novel method for calculating the Ceff of interconnect load for gate slew. We firstly establish a new expression for Ceff in 0.8Vdd point. Then the Integration Approximation method is used to calculate the value of Ceff in 0.8Vdd point. In this method, the integration of a complicated nonlinear gate output is approximated with that of a piecewise linear waveform. Based on the value of Ceff in 0.8Vdd point, Ceff of interconnect load for gate slew is obtained. The simulation results demonstrate a significant improvement in accuracy.

Finding DC operating points of nonlinear circuits is an important and difficult task. The Newton-Raphson method adopted in the SPICE-like simulators often fails to converge to a solution. To overcome this convergence problem, homotopy methods have been studied from various viewpoints. For the global convergence of homotopy methods, it is a necessary condition that a given initial solution is the unique solution to the homotopy equation. According to the conventional criterion, such an initial solution, however, is restricted in some very narrow region. In this paper, considering the circuit interpretation of homotopy equations, we prove theorems on the uniqueness of an initial solution for globally convergent homotopy methods. These theorems give new criteria extending the region wherein any desired initial solution satisfies the uniqueness condition.