A 60-GHz power amplifier (PA) with a reliability consideration for a hot-carrier-induced~(HCI) degradation is presented. The supply voltage of the last stage of the PA ($V_{{ m PA}}$) is dynamically controlled by an on-chip digitally-assisted low drop-out voltage regulator (LDO) to alleviate HCI effects. A physical model for estimation of HCI degradation of NMOSFETs is discussed and investigated for dynamic operation. The PA is fabricated in a standard 65-nm CMOS process with a core area of 0.21,mm$^{2}$, which provides a saturation power of 10.1,dBm to 13.2,dBm with a peak power-added efficiency~(PAE) of 8.1% to 15.0% for the supply voltage $V_{{ m PA}}$ which varies from 0.7,V to 1.0,V at 60,GHz, respectively.