Demands for the low power VLSI have been pushing the development of aggressive design methodologies to reduce the power consumption drastically. To meet the growing demand, we propose low power adders that adaptively select supply voltages based on the input vector patterns. First, we apply the proposed scheme to the Ripple Carry Adder (RCA). A prototype design by a 0.18 µm CMOS technology shows that the Adaptive VDD 32-bit RCA achieves 25% power improvement over the conventional RCA with similar speed. The proposed adder cancels out the delay penalty, utilizing two innovative techniques: carry-skip techniques on the checking operands, and the use of Complementary Pass Transistor Logic (CPL) with dual supply voltage for level conversion. As an expansion to faster adder architectures, we extend the proposal to the Carry-Select Adders (CSA) composed of the RCA sub-blocks. We achieved 24% power improvement on the 128-bit CSA prototype over a conventional design. The proposed scheme also achieves stand-by leakage power reduction--for 32-bit and 128-bit Adaptive RCA and CSA, respectively, 62% and 54% leakage reduction was possible.

This letter presents a method for reducing power dissipation in a protocol converter. The communication protocol of a VLSI chip hierarchically consists of several sub-protocols and only one of them can be actively working at any given time. In general, protocol converters are implemented by dual protocols of the initially given protocols which are to be interfaced. If the duals of those sub-protocols are implemented in separate modules, we can separate active modules and inactive modules on the fly since only one of the modules can be active at a time. The active/inactive state of a module can be monitored by the control signals that represent the execution of the protocol corresponding to the module. Power reduction can be achieved by dynamically suppressing the clock supply to inactive modules. To trade-off the power reduction rate against the area overhead, the module granularity must be properly chosen. For this purpose, we implement the duals of the atomic protocols in the same module if their state graphs share states except the initial state. Our experimental results show that this method provides significant savings in power consumption of between 18.4% and 92.1% with a 5.3% area overhead.