In this paper, a generalized Montgomery multiplication algorithm in GF(2m) using the Toeplitz matrix-vector representation is presented. The hardware architectures derived from this algorithm provide low-complexity bit-parallel systolic multipliers with trinomials and pentanomials. The results reveal that our proposed multipliers reduce the space complexity of approximately 15% compared with an existing systolic Montgomery multiplier for trinomials. Moreover, the proposed architectures have the features of regularity, modularity, and local interconnection. Accordingly, they are well suited to VLSI implementation.

Normal and dual bases are two popular representation bases for elements in GF(2m). In general, each distinct representation basis has its associated different hardware architecture. In this paper, we will present a unified systolic array multiplication architecture for both normal and dual bases, such a unified multiplication architecture is termed a Hankel multiplier. The Hankel multiplier has lower space complexity while compared with other existing normal basis multipliers and dual basis multipliers.

This investigation proposes a new multiplication algorithm in the finite field GF(2m) over the polynomial basis, in which the irreducible xm +xn + 1 with gcd(m,n) = 1 generates the field GF(2m). The algorithm involves two steps--the intermediate multiplication and the modulo reduction. In the first step, the intermediate multiplication algorithm permutes a polynomial to construct the full-bit-parallel systolic intermediate multiplier. The circuit is identical of m2 cells, each cell is identical of one 2-input AND gate, one 2-input XOR gate, and four 1-bit latches. In the second step, based on the results of the intermediate multiplication in the first step, the modulo reduction circuit is built using regular and simple reduction operations. The latency of the proposed multiplier requires m + k + 1 clock cycles, where k = + 1. Notably, the latency can be very low if n is in the range 1 n . For the computing multiplication in GF(2m), the novel multiplier exhibits much lower latency than the existing systolic multipliers, and is well suited to VLSI systems due to their regular interconnection pattern, modular structure and fully inherent parallelism.