Multiport SRAMs are frequently installed in network and/or telecommunication VLSIs to implement smart functions. This paper presents a high speed and low-power dual-port (i.e., 1W+1R two-port) SRAM macro customized for serial access operations. To reduce the wasted power dissipation due to subthreshold leakage currents, the supply voltage for 10T memory cells is lowered to 1 V and a power switch is prepared for every 64 word drivers. The switch is activated with look-ahead decoder-segment activation logic, so there is no penalty when selecting a wordline. The data I/O circuitry with a new column-based configuration makes it possible to hide the bitline precharge operation with the sensing operation in the read cycle ahead of it; that is, we have successfully reduced the read latency by a half clock cycle, resulting in a pure two-stage pipeline. The SRAM macro installed in a 4K-entry × 33-bit FIFO memory, fabricated with a 0.3-µm fully-depleted-SOI CMOS process, achieved a 500-MHz operation in the typical conditions of 2- and 1-V power supplies, and 25°C. The power consumption during the standby time was less than 1.0 mW, and that at a practical operating frequency of 400 MHz was in a range of 47-57 mW, depending on the bit-stream data pattern.

An ultra low power CMOS SAW oscillator in the 300-MHz-band that operates on a sub-1 V supply voltage and at sub-1 mW power consumption has been developed. The SAW oscillator is fabricated in a 0.35-µm fully depleted SOI (FD-SOI) process with low voltage operation capability. The SAW oscillator is configured as a type of Colpitts oscillator but consists of 3 cascaded amplifiers instead of a single amplifier. Although the circuit configuration is quite similar to the conventional Colpitts oscillator, this proposed configuration generates an excessively high negative resistance that even exceeds the theoretical limit of the conventional one.