With the increase of commercial multimedia applications using digital video, the security of video data becomes more and more important. Although several techniques have been proposed in order to protect these video data, they provide limited security or introduce significant overhead. This paper proposes a video security scheme for MPEG video compression standard, which includes two methods: DCEA (DC Coefficient Encryption Algorithm) and "Event Shuffle." DCEA is aim to encrypt group of codewords of DC coefficients. The feature of this method is the usage of data permutation to scatter the ciphertexts of additional codes in DC codewords. These additional codes are encrypted by block cipher previously. With the combination of these algorithms, the method provides enough security for important DC component of MPEG video data. "Event Shuffle" is aim to encrypt the AC coefficients. The prominent feature of this method is a shuffling of AC events generated after DCT transformation and quantization stages. Experimental results show that these methods introduce no bit overhead to MPEG bit stream while achieving low processing overhead to MPEG codec.

Future wireless/mobile system is expected to have heterogeneous wireless overlay networks for ubiquitous multimedia communication. In a such network environment, mobile users are likely to try to get attached to higher bandwidth network as bandwidth-hungry multimedia applications are increasing. However, the users have to perform vertical handoff to lower bandwidth network, as high bandwidth network become unavailable due to various reasons (such as its limited coverage, network congestion, etc.). In this paper, we discuss the problem of vertical handoff from a user's perspective. For this purpose, we formulate user satisfaction as a function of bandwidth utility and handoff latency. Then, we investigate the effect of call holding time, user movement probability, etc. on the satisfaction that a user derives from the use of network service for multimedia applications. In addition, based on the evaluation, we present an algorithm for selecting a wireless network, which maximizes the effective user satisfaction.

In this paper, two efficient VLSI architectures for biorthogonal wavelet transform are proposed. One is constructed by the filter bank implementation and another is constructed by the lifting scheme. In the filter bank implementation, due to the symmetric property of biorthogonal wavelet transform, the proposed architecture uses fewer multipliers than the orthogonal wavelet transform. Besides, the polyphase decomposition is adopted to speed up the processing by a factor of 2. In the lifting scheme implementation, the pipeline-scheduling technique is employed to optimize the architecture. Both two architectures are with advantages of lower implementation complexity and higher throughput rate. Moreover, they can also be applied to realize the inverse DWT efficiently. Based on the above properties, the two architectures can be applied to time-critical image compressions, such as JPEG2000. Finally, the architecture constructed by the lifting scheme is implemented into a single chip on 0.35 µm 1P4M CMOS technology, and its area and working performance are 5.005 5.005 mm2 and 50 MHz, respectively.

In this paper, a high-performance pipelining architecture for 2-D inverse discrete wavelet transform (IDWT) is proposed. We use a tree-block pipeline-scheduling scheme to increase computation performance and reduce temporary buffers. The scheme divides the input subbands into several wavelet blocks and processes these blocks one by one, so the size of buffers for storing temporal subbands is greatly reduced. After scheduling the data flow, we fold the computations of all wavelet blocks into the same low-pass and high-pass filters to achieve higher hardware utilization and minimize hardware cost, and pipeline these two filters efficiently to reach higher throughput rate. For the computations of N N-sample 2-D IDWT with filter length of size K, our architecture takes at most (2/3)N2 cycles and requires 2N(K-2) registers. In addition, each filter is designed regularly and modularly, so it is easily scalable for different filter lengths and different levels. Because of its small storage, regularity, and high performance, the architecture can be applied to time-critical image decompression.

In this paper, a VLSI architecture for lifting-based discrete wavelet transform (LDWT) is presented. Our architecture folds the computations of all resolution levels into the same low-pass and high-pass units to achieve higher hardware utilization. Due to the regular and flexible structure of the design, its area is independent of the length of the 1-D input sequence, and its latency is independent of the number of resolution levels. For the computations of analysis process of N-sample 1-D 3-level LDWT, our design takes about N clock cycles and requires 2 multipliers, 4 adders, and 22 registers. It is fabricated with TSMC 0.35-µm cell library and has a die size of 1.21.2 mm2. The power dissipation of the chip is about 0.4 W at the clock rate of 80 MHz.

Distributed multimedia applications are often sensitive to the Quality of Service (QoS) provided by the communication network. They usually require guaranteed QoS service, so that real-time communication is possible. However, searching a route with multiple QoS constraints is known to be a NP-complete problem. In this paper, we propose a new simple and efficient distributed QoS routing algorithm, called "DQoSR," for supporting real-time communication in high-speed networks. It searches a route that could guarantee bandwidth, delay, and delay jitter requirements. Routing decision is based only on the modified cost, hop and delay vectors stored in the routing table at each node and its directly connected neighbors. Moreover, DQoSR is proved to construct loop-free routes. Its worst case message complexity is O(|V|2), where |V| is the number of nodes in the network. Thus DQoSR is fast and scales well to large networks. Finally, extensive simulations show that average rate of establishing successful connection of DQoSR is very near to optimum (the difference is less than 0.4%).