This paper demonstrates a quick start method for Pulse-Width Controlled PLL (PWPLL). Our PLL converts the internal state into digital signals and stores them into a memory before getting into a sleep mode. The wakeup sequence reads the memory and presets the internal state so that our PLL can start the operation with close to the previously locked condition. Since the internal state includes not only the frequency control code but also the phase information, our quick start PLL locks in several clock cycles. A prototype chip fabricated in 0.18µm standard CMOS shows 50ns settling time (4 reference clock cycles), 18.5mW power consumption under 1.8V nominal supply voltage with 105µm×870µm silicon area.

This paper proposes a self frequency preset (SFP) PLL synthesizer to realize a simple frequency preset PLL synthesizer with temperature-resistant and shorter frequency settling time than the conventional temperature un-compensated phase and frequency preset (PFP) PLL synthesizer. Since the proposed synthesizer employs a simple frequency locked loop (FLL) circuit to preset the output frequency at each frequency hopping period, the synthesizer eliminates the need to store f-V characteristic of the VCO in ROM. The frequency settling time of the proposed synthesizer is theoretically and experimentally analyzed. The theoretical analysis using the realistic f-V characteristic of a IF band VCO show that the frequency settling time of the proposed synthesizer is 130µs shorter than that of the conventional PFP PLL synthesizer at 40MHz hopping in the 200MHz band for all temperatures. Furthermore, the experimental results confirm that the frequency acquisition time of a prototype FLL circuit is accordant with the calculated results. Thus, the proposed SFP PLL synthesizer can achieve faster frequency settling than the conventional PFP PLL synthesizer for all temperatures and its simple configuration allows to be easily implemented with existing CMOS ASIC devices.