Novel low phase noise quadrature voltage-controlled oscillator (QVCO) and quadrature injection locked frequency divider (QILFD) with two coupled Hartley VCOs are proposed and implemented using the standard TSMC 0.18 µm CMOS 1P6M process. The QVCO employs pMOS as the core to reduce the up-conversion of low-frequency device noise to RF phase noise. It uses super-harmonic coupling technique to couple two differential Hartley VCOs and four small-size coupling transistors to set the directivity of quadrature output phases. At the 1.7 V supply voltage, the output phase noise of the QVCO is -124 dBc/Hz at 1 MHz offset frequency from the carrier frequency of 4.12 GHz, and the figure of merit is -185 dBc/Hz. At the supply voltage of 1.7 V, the total power consumption is 13.1 mW. At the supply voltage of 1.5 V, the tuning range of the free-running QILFD is from 2.05 GHz to 2.36 GHz, about 310 MHz, and the locking range of the ILFD is from 3.99 to 5.19 GHz, about 1.20 GHz, at the injection signal power of 0 dBm.

A complementary cross-coupled differential Colpitts voltage controlled oscillator (VCO) is reported. The combination of gm-boosting and the complementary transistors allows record low power integrated VCO implementation. The proposed VCO and the corresponding parallel quadrature VCO (P-QVCO) are implemented using 0.25-µm CMOS technology for 1.8 GHz operation. Measurements for the VCO and P-QVCO show phase noise of -116.8 and -117.7 dBc/Hz at 1 MHz offset, while dissipating only 0.4 and 1.1 mA from a 0.9-V supply, respectively.