A novel NiSi technology with bi-layer Co/TiN structure as a capping layer is proposed for the highly thermal immune Ni Silicide technology. Much better thermal immunity of Ni Silicide was certified up to 700, 30 min post silicidation furnace annealing by introducing Co/TiN bi-layer capping. The proposed structure is successfully applied to nano-scale CMOSFET with a gate length of 80 nm. The sheet resistance of nano-scale gate poly shows little degradation even after the high temperature furnace annealing of 650, 30 min. The Ni/Co/TiN structure is very promising for the nano-scale MOSFET technology which needs the ultra shallow junction and high temperature post silicidation processes

In this letter, a method to construct good binary and quaternary error correcting codes, called complex Hadamard codes, based on a complex Hadamard matrix is presented. The related properties of the codes are analyzed. In addition, through the operation in Z4 domain, a new simplex soft-decision decoding algorithm for the complex Hadamard codes is also proposed.

A new class of ternary sequence having a zero-correlation zone (zcz), based on Hadamard matrices, is presented. The proposed sequence construction can simultaneously generate a finite-length ternary zcz sequence set and a periodic ternary zcz sequence set. The generated finite-length ternary zcz sequence set has a zero-correlation zone for an aperiodic function. The generated periodic ternary zcz sequence set has a zero-correlation zone for even and odd correlation functions.

Relative time-stamping schemes prove the chronological sequence of digital documents and their integrity. Since the chronological sequence is verified by tracing the link between two timestamps, it is desirable that the length of the verification path is short. Buldas, Laud, Lipmaa, and Villemson have proposed the relative time-stamping scheme based on the binary link. In this paper, we extend the binary link to the ternary link, and apply it to the relative time-stamping scheme. We show that the maximum length of the verification path of the proposed scheme is shorter than that of the previous scheme. Moreover, we show that the average length of the proposed scheme is shorter than that of the previous scheme. Thus, the proposed time-stamping schemes is more efficient than the previous scheme.

The present letter introduces a new approach to the construction of a set of ternary arrays having a zero-correlation zone. The proposed array set has a zero-correlation zone for both periodic and aperiodic correlation functions. As such, the proposed arrays can be used as a finite-size array having a zero-correlation zone. The proposed array sets can be constructed from an arbitrary Hadamard matrix. The member size of the proposed array set is close to the theoretical upper bound.

The present paper introduces a new approach to the construction of a class of ternary sequences having a zero-correlation zone. The cross-correlation function of each pair of the proposed sequences is zero for phase shifts within the zero-correlation zone, and the auto-correlation function of each proposed sequence is zero for phase shifts within the zero-correlation zone, except for zero-shift. The proposed sequence set has a zero-correlation zone for periodic, aperiodic, and odd correlation functions. As such, the proposed sequence can be used as a finite-length sequence with a zero-correlation zone. A set of the proposed sequences can be constructed for any set of Hadamard sequences of length n. The constructed sequence set consists of 2n ternary sequences, and the length of each sequence is (n+1)2m+2 for a non-negative integer m. The periodic correlation function, the aperiodic correlation function, and the odd correlation function of the proposed sequences have a zero-correlation zone from -(2m+1-1) to (2m+1-1). The member size of the proposed sequence set is of the theoretical upper bound of the member size of a sequence having a zero-correlation zone. The ratio of the number of non-zero elements to the the sequence length of the proposed sequence is also .

Some of the recent digital systems have a serious clock skew problem due to huge hardware implementation and high-speed operation in VLSI's. To overcome this problem, clock distribution techniques and, more notably, asynchronous system design methodologies have been investigated. Since the latest asynchronous digital systems use two-rail logic with two-phase data transfer manner, more than two-fold hardware is required in comparison with the synchronous system. In this article, we present a design of asynchronous digital system which is based on B-ternary logic that can process binary data. The system which is based on speed-independent mode consists of data-path and its controller. Then we provide B-ternary two-phase binary data processing in the data-path and its control procedure with hand-shake protocol. To implement the system some functional elements are presented, that is, a ternary-in/binary-out register with request/acknowledge circuits and a control unit. These functional elements are fabricated with ternary NOR, NAND, INV gates and ternary-in/binary-out D-FF (D-elements). The B-ternary based asynchronous circuit has less interconnections, achives race-free operations and makes use of conventional binary powerful design tools. Particularly, we extend the speed-independent delay model to relativity delays in order to reduce hardware overhead of checking memory stability in the system. As a concrete example, a carry-completion type asynchronous adder system is demonstrated under extended speed-independent mode to show the validity of the extension.

Regular ternary logic functions are one of the most useful special classes of Kleenean functions, and a lot of research has been done on them. However, there has been little work done on incompletely specified regular ternary logic functions. This paper describes the following points: (1) Minimization of incompletely specified regular ternary logic functions. (2) A new definition of incompletely specified fuzzy switching functions and their minimization. (Concretely speaking, minimal disjunctive forms of incompletely specified fuzzy switching functions are represented in formulas of regular ternary logic functions. ) (3) Their application to fuzzy logic circuits such as fuzzy PLAs of AND-OR type.

Three types of ternary decision diagrams (TDDs) are considered: AND -TDDs, EXOR-TDDs, and Kleene-TDDs. Kleene-TDDs are useful for logic simulation in the presence of unknown inputs. Let N(BDD:f), N(AND-TDD:f), and N(EXOR-TDD:f) be the number of non-terminal nodes in the BDD, the AND-TDD, and the EXOR-TDD for f, respectively. Let N(Kleene-TDD:) be the number of non-terminal nodes in the Kleene -TDD for , where is the regular ternary function corresponding to f. Then N(BDD:f) N(TDD:f). For parity functions, N(BDD:f)=N(AND-TDD:f)=N(EXOR-TDD:f)=N(Kleene-TDD:). For unate functions,N(BDD:f)=N(AND-TDD:f). The sizes of Kleene-TDDs are O(3n/n), and O(n3) for arbitrary functions, and symmetric functions, respectively. There exist a 2n-variable function, where Kleene-TDDs require O(n) nodes with the best order, while O(3n) nodes in the worst order.

Ordered Binary Decision Diagrams (OBDDs) are graph-based representations of Boolean functions which are widely used because of their good properties. In this paper, we introduce nondeterministic OBDDs (NOBDDs) and their restricted forms, and evaluate their expressive power. In some applications of OBDDs, canonicity, which is one of the good properties of OBDDs, is not necessary. In such cases, we can reduce the required amount of storage by using OBDDs in some non-canonical form. A class of NOBDDs can be used as a non-canonical form of OBDDs. In this paper, we focus on two particular methods which can be regarded as using restricted forms of NOBDDs. Our aim is to show how the size of OBDDs can be reduced in such forms from theoretical point of view. Firstly, we consider a method to solve satisfiability problem of combinational circuits using the structure of circuits as a key to reduce the NOBDD size. We show that the NOBDD size is related to the cutwidth of circuits. Secondly, we analyze methods that use OBDDs to represent Boolean functions as sets of product terms. We show that the class of functions treated feasibly in this representation strictly contains that in OBDDs and contained by that in NOBDDs.

In this paper, we propose a method to design ternary cellular arrays by using Ternary Decision Diagrams (TDD's). Our cellular array has a rectangular structure composed of ternary switch cells. The ternary functions represented by TDD's are realized by mapping the TDD's to the arrays directly. That is, both the nodes and the edges in the TDD are realized by some sets of the cells. Since TDD's can represent easily multiple-output functions without large memory requirements, our arrays are wuitable for the realization of multiple-output functions. To evaluate our method, we apply our method to some benchmark circuits, and compare our arrays with the ternary PLA's. The experimental results show that our arrays have the advantage for their sizes, especially in the realization of symmetric functions. The results also clarify that the size of our arrays depends on the size of TDD's.

A new design methodology is proposed and analyzed for the design of ternary logic systems. In the new ternary logic systems, no conversions among radices are required and only the two-state ternary literals associated with the ternary signals are transmitted in the whole system. With the new design methodology, the ternary systems can be realized by the dynamic CMOS logic circuits which are simple and fully compatible with those of the conventional binary logic circuits in process, power supply, and logic levels. A new dynamic differential logic called the CMOS Redundant Differential Logic (CRDL) is also developed to increase the logic flexibility and the circuit performance. Using the new design methodology and the CRDL circuits, the multiplier with redundant binary addition tree is designed in both non-pipelined and pipelined systems. The experimental chip has been fabricated and measured, which successfully verifies the correctness of the logic functions and the speed performance of the designed circuits.