By means of the three-dimensional (3D) finite-difference time domain (FDTD) method, we have investigated in detail the optical properties of a two-dimensional photonic crystal (PC) surface-emitting laser having a square-lattice structure. The 3D-FDTD calculation is carried out for the finite size PC slab structure. The device is based on band-edge resonance, and plural band edges are present at the corresponding band edge point. For these band edges, we calculate the mode profile in the PC slab, far field pattern (FFP) and polarization mode of the surface-emitted component, and photon lifetime. FFPs are shown to be influenced by the finiteness of the structure. Quality (Q) factor, which is a dimensionless quantity representing photon lifetime, is introduced. The out-plane radiation loss in the direction normal to the PC plane greatly influences the total Q factor of resonant mode and is closely related with the band structure. As a result, Q factors clearly differ among these band edges. These results suggest that these band edges include resonant modes that are easy to lase and resonant modes that are difficult to lase.

In order to investigate the jitter characteristics of PLLs for practical applications, we have developed a computer simulation program of PLL, which can deal with arbitrary patterns both of data and jitters, as well as a conceivable nonlinearity of the circuit performance. We used a time-domain method, namely, we solved the state equation of a charge pump type PLL with a constant time step. The jitter transfer characteristics of a conventional PLL were calculated for periodic input data patterns with sinusoidal jitters. The result agreed fairly well with the corresponding experiments. And we have revealed that an ordinary PD (Phase Detector), which detects the phase difference between input and VCO signals at only rising edges, shows the folded jitter transfer characteristics at the half of the equivalent frequency of the input signal. This folded jitter characteristics increases the total jitter for long successive '1' or '0' data patterns, because of their low equivalent sampling frequency, and might increase the jitter even for the random data patterns. Based on simulation results, we devised an improved phase detector for PLL having a low jitter characteristics. And we also applied the simulation to an FDD (Frequency Difference Detector) type fast pull-in PLL which we have proposed recently, and obtained that the jitter of it was smaller than that of a conventional PLL by 25% for PRBS (pseudo random bit sequence) NRZ code.