A High-Speed ATM Switching Architecture Using Small Shared Switch Blocks

Ken-ichi ENDO; Naoaki YAMANAKA

A High-Speed ATM Switching Architecture Using Small Shared Switch Blocks

Ken-ichi ENDO, Naoaki YAMANAKA

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This paper proposes a compact high-speed ATM switching architecture that employs a novel arbitration method. The NN matrix shaped crosspoint switch is realized with D small switch blocks (SSBs). The number of crosspoints and address comparators is reduced from N² to (N/D)². Each block contains N/D input lines and N/D output lines. The association between output lines and output ports is logically changed each cell period. This arrangement permits each input port to be connected to N/D output ports in each cell period. Output-line contention control is realized block-by-block so high-speed operation is realized. The traffic characteristics of the proposed switch architecture are analyzed using computer simulations. According to the simulation results, the cell loss rate of 10^-8 is achieved with only 100-cell input and output-buffers under the heavy random load of 0.9 for any size switch. The proposed ATM switching architecture can construct the Gbit/s high-speed ATM switch fabric needed for B-ISDN.

Publication: IEICE TRANSACTIONS on Communications Vol.E76-B No.7 pp.736-740

Publication Date: 1993/07/25

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Type of Manuscript: Special Section LETTER (Special Section of Letters Selected from the 1992 IEICE Fall Conference and the 1993 IEICE Spring Conference)

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Ken-ichi ENDO, Naoaki YAMANAKA, "A High-Speed ATM Switching Architecture Using Small Shared Switch Blocks" in IEICE TRANSACTIONS on Communications, vol. E76-B, no. 7, pp. 736-740, July 1993, doi: .
Abstract: This paper proposes a compact high-speed ATM switching architecture that employs a novel arbitration method. The NN matrix shaped crosspoint switch is realized with D small switch blocks (SSBs). The number of crosspoints and address comparators is reduced from N² to (N/D)². Each block contains N/D input lines and N/D output lines. The association between output lines and output ports is logically changed each cell period. This arrangement permits each input port to be connected to N/D output ports in each cell period. Output-line contention control is realized block-by-block so high-speed operation is realized. The traffic characteristics of the proposed switch architecture are analyzed using computer simulations. According to the simulation results, the cell loss rate of 10^-8 is achieved with only 100-cell input and output-buffers under the heavy random load of 0.9 for any size switch. The proposed ATM switching architecture can construct the Gbit/s high-speed ATM switch fabric needed for B-ISDN.
URL: https://globals.ieice.org/en_transactions/communications/10.1587/e76-b_7_736/_p

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@ARTICLE{e76-b_7_736,
author={Ken-ichi ENDO, Naoaki YAMANAKA, },
journal={IEICE TRANSACTIONS on Communications},
title={A High-Speed ATM Switching Architecture Using Small Shared Switch Blocks},
year={1993},
volume={E76-B},
number={7},
pages={736-740},
abstract={This paper proposes a compact high-speed ATM switching architecture that employs a novel arbitration method. The NN matrix shaped crosspoint switch is realized with D small switch blocks (SSBs). The number of crosspoints and address comparators is reduced from N² to (N/D)². Each block contains N/D input lines and N/D output lines. The association between output lines and output ports is logically changed each cell period. This arrangement permits each input port to be connected to N/D output ports in each cell period. Output-line contention control is realized block-by-block so high-speed operation is realized. The traffic characteristics of the proposed switch architecture are analyzed using computer simulations. According to the simulation results, the cell loss rate of 10^-8 is achieved with only 100-cell input and output-buffers under the heavy random load of 0.9 for any size switch. The proposed ATM switching architecture can construct the Gbit/s high-speed ATM switch fabric needed for B-ISDN.},
keywords={},
doi={},
ISSN={},
month={July},}

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TY - JOUR
TI - A High-Speed ATM Switching Architecture Using Small Shared Switch Blocks
T2 - IEICE TRANSACTIONS on Communications
SP - 736
EP - 740
AU - Ken-ichi ENDO
AU - Naoaki YAMANAKA
PY - 1993
DO -
JO - IEICE TRANSACTIONS on Communications
SN -
VL - E76-B
IS - 7
JA - IEICE TRANSACTIONS on Communications
Y1 - July 1993
AB - This paper proposes a compact high-speed ATM switching architecture that employs a novel arbitration method. The NN matrix shaped crosspoint switch is realized with D small switch blocks (SSBs). The number of crosspoints and address comparators is reduced from N² to (N/D)². Each block contains N/D input lines and N/D output lines. The association between output lines and output ports is logically changed each cell period. This arrangement permits each input port to be connected to N/D output ports in each cell period. Output-line contention control is realized block-by-block so high-speed operation is realized. The traffic characteristics of the proposed switch architecture are analyzed using computer simulations. According to the simulation results, the cell loss rate of 10^-8 is achieved with only 100-cell input and output-buffers under the heavy random load of 0.9 for any size switch. The proposed ATM switching architecture can construct the Gbit/s high-speed ATM switch fabric needed for B-ISDN.
ER -